Comments (1)
Recommended reading: R. Neugebauer, G. Antichi, J. Zazo, Y. Audvevich, S. López-Buedo, A. Moore, Understanding PCIe performance for end host networking, SIGCOMM 2018
The paper isn't available yet, it will probably appear by early July.
They've done some really interesting experiments there (I read an earlier draft last year). I'm sure the authors are happy to share a pre-print with you if you ask nicely.
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Related Issues (14)
- Define Transmit interface HOT 4
- Podcast with Hennessy and Patterson about RISC
- Support multiple read/write cores efficiently
- Benchmark setup for validating design HOT 11
- Hard to keep up with the concepts! HOT 2
- [Mildy interesting] NIC speed vs. driver lines of code HOT 7
- Hardware for 10G EasyNIC HOT 6
- How a ConnectX device driver works [FOSDEM talk]
- Define the Receive interface
- Avoid individual descriptors HOT 3
- Consider adding TX_BLOCK_SIZE register HOT 2
- Eliminate read from transmit path HOT 1
- Avoid streaming non-idempotent register writes? HOT 1
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