lvd2 / ay-3-8910_reverse_engineered Goto Github PK

The reverse-engineered AY-3-8910 chip. Transistor-level schematics, verilog model and a testbench with tools, that can render register dump files into .flac soundtrack.

License: GNU General Public License v3.0

Verilog 90.97% Shell 1.26% Python 7.77%

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mrdion nicopy jotego loesterfranco nsbajakian moneytech 3lvd mfkiwl jtfpga 00mjk steamgamemodder

ay-3-8910_reverse_engineered's Issues

Used your model

This is not really an issue. Just to tell you that I used your model to verify my FPGA oriented core JT49 and it helped me find two bugs. I also changed the phase of the noise signal. The phase change will not make a difference on the sound but, well, just to be accurate.

You can have a look at how I built the simulation in the ver/comp folder in case you are curious. This is the commit. https://github.com/jotego/jtframe/commit/d39f3e7451c1c1b5a44e79de8d99285d3c73e693

Thank you
Jotego

ay_model.v gets crazy when rst_n ends at positive edge of clk

Clock dividers get crazy in this case.
To fix, delay rst_n deassertion several nans from posedge of clk.

Multi page PDF, please

I am not able to really browse the schematics, using the PDF file. It is just too large. I've trying importing it into other tools but I never get good results. Could you add multi page schematics in PDF please?

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