maehw / wokwi-lookup-table-generator Goto Github PK

{
  "version": 1,
  "description": "Generates patterns.",
  "inputs": ["t", "u"],
  "outputs": {
    "A": [1, 0, 0, 0],
    "G": [0, 0, 0, 1]
  }
}

$ python3 generate.py -v -f logic.json -o logic.wokwi
[    INFO] Log level: INFO
[    INFO] Data is read from input file 'logic.json'
[    INFO] Inputs:     2 ['t', 'u']
[    INFO] Outputs:    2 ['A', 'G']
[    INFO]   Output A: [1, 0, 0, 0]; ones: [0]
[    INFO]   Output G: [0, 0, 0, 1]; ones: [3]
Traceback (most recent call last):
  File "/home/osboxes/src/wokwi-lookup-table-generator/generate.py", line 441, in <module>
    logic_meta[output]["qm_terms_raw"] = list( q.simplify(logic[output]) ) # convert set into list (to allow indexing)
  File "/home/osboxes/venvs/py/lib/python3.9/site-packages/quine_mccluskey/qm.py", line 130, in simplify
    return self.simplify_los(ones, dc)
  File "/home/osboxes/venvs/py/lib/python3.9/site-packages/quine_mccluskey/qm.py", line 193, in simplify_los
    essential_implicants = self.__get_essential_implicants(prime_implicants, set(dc))
  File "/home/osboxes/venvs/py/lib/python3.9/site-packages/quine_mccluskey/qm.py", line 419, in __get_essential_implicants
    perms[t] = set(p for p in self.permutations(t) if p not in dc)
  File "/home/osboxes/venvs/py/lib/python3.9/site-packages/quine_mccluskey/qm.py", line 419, in <genexpr>
    perms[t] = set(p for p in self.permutations(t) if p not in dc)
  File "/home/osboxes/venvs/py/lib/python3.9/site-packages/quine_mccluskey/qm.py", line 532, in permutations
    if value[i] == '0' or value[i] == '1':
IndexError: string index out of range

    "A": [0, 0, 1, 0],

$ python3 generate.py -v -f logic.json -o logic.wokwi
[    INFO] Log level: INFO
[    INFO] Data is read from input file 'logic.json'
[    INFO] Inputs:     2 ['t', 'u']
[    INFO] Outputs:    2 ['A', 'G']
[    INFO]   Output A: [0, 0, 1, 0]; ones: [2]
[    INFO]   Output G: [0, 0, 0, 1]; ones: [3]
[    INFO] Calculated CNF for output A: t~u
[    INFO] Calculated CNF for output G: tu
[    INFO] Estimated parts usage:
[    INFO]     *   4 buffers (for the inputs and the outputs)
[    INFO]     *   2 NOT gate(s) (for the negated inputs)
[    INFO]     *   2 two-input AND gate(s), in max. 1 stages
[    INFO]     * number of two-input OR gate(s) not estimated yet
[    INFO] 
[    INFO] Connecting inputs with first stage of AND gates for every output.
[    INFO] Connecting input inside the wokwi design to first AND gate stage (later used for output A)...
[    INFO] All AND gates required in the first AND gate stage for output A: [[0]]
[    INFO] Connecting input inside the wokwi design to first AND gate stage (later used for output G)...
[    INFO] All AND gates required in the first AND gate stage for output G: [[1]]
[    INFO] Connecting inputs with first stage of AND gates for every output completed.
[    INFO] 
[    INFO] Merges all first stage AND gates down to a single 'root' AND gate (for every term of every output)
[    INFO] Single AND gate #0 does not need to be merged.
[    INFO] Remaining AND gates (final stage): [0] for the output A to be connected to OR gates
[    INFO] Single AND gate #1 does not need to be merged.
[    INFO] Remaining AND gates (final stage): [1] for the output G to be connected to OR gates
[    INFO] Merges of all first stage AND gates down to a single 'root' AND gate completed.
[    INFO] 
[    INFO] Combining mini terms: Create first stage of OR gates (in order to OR all terms for every output) 
[    INFO] and connect the AND gate from the previous stage (=the final AND stage) to it.
[ WARNING] Single mini term for output A: AND gate output (AND gate #0)
[ WARNING] Creating a dummy OR gate (which does not need to be then merged down).
[    INFO] First stage of OR gates (connected to AND gates): [0] for output A
[ WARNING] Single mini term for output G: AND gate output (AND gate #1)
[ WARNING] Creating a dummy OR gate (which does not need to be then merged down).
[    INFO] First stage of OR gates (connected to AND gates): [1] for output G
[    INFO] Done combining mini terms (AND gates) by first stage of OR gates.
[    INFO] 
[    INFO] Merges all first stage OR gates down to a single 'root' OR gate and connect them to the output buffers
[    INFO] Performing the merges of all OR gates for output A
[    INFO] Number of OR gates to be merged: 1, i.e. [0]
[    INFO] Only single OR gate, therefore directly connect it to the output buffer
[    INFO] Identified #0 as final OR gate for the output A to be connected to output buffer
[    INFO] Performing the merges of all OR gates for output G
[    INFO] Number of OR gates to be merged: 1, i.e. [1]
[    INFO] Only single OR gate, therefore directly connect it to the output buffer
[    INFO] Identified #1 as final OR gate for the output G to be connected to output buffer
[    INFO] Max AND gate stages: 1
[    INFO] Max  OR gate stages: 1
[    INFO] Finished the wokwi design!
[    INFO] Writing final wokwi design file 'logic.wokwi'...

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     "type": "wokwi-dip-switch-8",
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     "top": -178.4,
     "left": -102.9,
     "rotate": 90,
     "attrs": {}
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   {
     "type": "wokwi-clock-generator",
     "id": "clock1",
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   },
   { "type": "wokwi-gnd", "id": "pwr2", "top": -76.8, "left": 892.2, "attrs": {} },
   { "type": "wokwi-vcc", "id": "pwr1", "top": -229.64, "left": -115.2, "attrs": {} },
   {
     "type": "chip-input-8-pins",
     "id": "chip1",
     "top": -190.98,
     "left": -4.8,
     "attrs": { "verilogRole": "input" }
   },
   {
     "type": "chip-output-8-pins",
     "id": "chip2",
     "top": -190.98,
     "left": 686.4,
     "attrs": { "verilogRole": "output" }
   },
   {
     "type": "wokwi-7segment",
     "id": "sevseg1",
     "top": -183.24,
     "left": 878.68,
     "attrs": { "common": "cathode" }
   },
   {
     "type": "wokwi-slide-switch",
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     "top": -302.8,
     "left": -35.3,
     "attrs": { "value": "1" }
   },
   {
     "type": "wokwi-pushbutton",
     "id": "btn1",
     "top": -354.6,
     "left": -146,
     "attrs": { "color": "grey", "label": "Step", "bounce": "0" }
   }