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Self checking RISC-V directed tests

Shell 11.62% Python 88.38%

tenstorrent_riscv_arch_tests's Introduction

Welcome to MANAV SHAH's Git page

About

  • ๐ŸŽ“ MS Computer Engineering, Virginia Tech.

  • ๐ŸŽ“ B-Tech in Electronics and Telecommunication Engineering, Veermata Jijabai Technological Institute.

  • ๐Ÿ† Winner of Smart India Hackathon 2023 (Hardware edition)

  • ๐Ÿ’ผ Ex VYOMA Systems RISCV V Verification Intern.

Publication

IEEE ANTS 2023: Reliable key generation for authentication and encryption using RO PUF on FPGA

Research Interests

  • Digital Design and Verification
  • Hardware Descriptive Languages - Verilog / VHDL.
  • anythihg and everything on FPGAs.

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chenhuangtt avatar darshakk avatar mbrotherstt avatar

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