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labs-with-cva6

Advanced Architecture Labs with CVA6

miaow

An open source GPU based off of the AMD Southern Islands ISA.

ml-for-beginners

12 weeks, 24 lessons, classic Machine Learning for all

noculator

NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, hierarchical ring, flattened butterfly) and routers (buffered, bufferless, Adaptive Flow Control, minBD, HiRD).

nyuziprocessor

GPGPU microprocessor architecture

openpiton

The OpenPiton Platform

pasc

Parallel Array of Simple Cores. Multicore processor.

r-vex

A reconfigurable and extensible VLIW processor implemented in VHDL

regular_expressions

This Repository illustrates the Regular Expressions that are useful in reading the files with respect to Chip Design

ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

risc-v-vector

Vector processor for RISC-V vector ISA

riscv-crypto

RISC-V cryptography extensions standardisation work.

riscv-formal

RISC-V Formal Verification Framework

riscv-myth_workshop

RISCV-MYTH-Workshop-August-ManjunathKalmath created by GitHub Classroom

riscv-rv32i

Hardware implementation of RV32I

sanctum

The MIT Sanctum processor top-level project

simpletpu

A FPGA Based CNN accelerator, following Google's TPU V1.

sky130rtl

sky130sta

sparse-matrix

C++ implementation of sparse matrix using CRS (Compressed Row Storage) format

tomasulo-architecture

Simulation of the Tomasulo algorithm using python and verilog.Python code has been included to simulate dynamic instruction scheduling.This project was done as the part of Computer Architecture course.

tool_command_language

This repository contains basics of TCL hands on

xtensa-fft

Hardware accelerated Cooley-Tukey FFT implementation for the Xtensa architecture.