mars4zhu / vsrtl

Visual Simulation of Register Transfer Logic

VSRTL

Visual Simulation of Register Transfer Logic

VSRTL is a collection of libraries and applications for visualizing simulations of digital circuits. VSRTL is intended to be an intuitive HDL simulator which may be used for teaching digital circuits and boolean logic.

Refer to the reference section for implementation and usage documentation.
If you would like to contribute, check the issues section - There's plenty of work to be done!

Figure: A simulation of a 3-bit counter utilizing 3 full adders. Note; placement and routing have not yet been implemented, and as such component placement in this image is manual, and signals are drawn as straight lines from source to sinks.

Building

With the dependencies installed, open vsrtl/CMakeLists.txt as a CMake project in your favourite editor, run CMake and build app.cpp.

Dependencies:

• Core
  • C++14 toolchain
  • CMake
• Graphics
  • Qt 5.9.3+: https://www.qt.io/download