riscv-sim's Introduction

RISC-V Sim

A simulation of a simple RISC-V computer

Getting Started

Installing

This project requires cargo to be installed which can be downloaded from the rust website.

Running

Once rust is installed the library can then be tested using

cargo test

A RISC machine can then be made by providing an already created registry and memory

let mut memory = Memory::default();
memory.set_four_byte(u20::new(0), 100);
let mut registry = Registry::default();
registry.set(rs1, 100);

let mut machine = RISCMachine {
    memory,
    registry,
    program_counter: u20::new(0),
};

or by simply loading the memory into an empty machine

let mut memory = Memory::default();

let mut machine = RISCMachine::default();
machine.load_memory(memory);

The machine currently supports 8 instructions

pub enum CPUInstruction {
    ADD { rd: u5, rs1: u5, rs2: u5 },
    SUB { rd: u5, rs1: u5, rs2: u5 },
    LW { rd: u5, rs1: u5, imm: u32 },
    SW { rs1: u5, rs2: u5, imm: u32 },
    JAL { rd: u5, imm: u32 },
    JALR { rd: u5, rs1: u5, imm: u32 },
    BEQ { rs1: u5, rs2: u5, imm: u32 },
    BNE { rs1: u5, rs2: u5, imm: u32 },
}

A detailed description of each instruction can be found here.

The machine can be ran one tick at a time, or until the program counter reaches a specific value

//Process a single instruction
machine.tick()?;

//Process until the program counter reaches 10
machine.run(&|pc| -> bool { pc == u20::new(10) })?;

Acknowledgments

This simulation took inspiration from the Tiny RISC-V architecture, which is a simple subset of the complete RISC-V specification which can be found here.

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