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A 16 bit microprocessor (Microprocessor without Interlocked Pipeline Stages - MIPS) programmed (in Verilog) and designed in Xilinx ISE.

Verilog 14.40% HTML 2.02% VHDL 4.77% Batchfile 0.56% Shell 1.41% Tcl 2.16% Stata 0.61% SystemVerilog 0.08% C 73.97%

16-bit-mips's Introduction

  • 👋 Heyy, I’m Meet working as a Software Engineer in India.
  • 👀 I’m into Backend dev, but sometimes I do Full-Stack dev too.
  • 📫 I often wander on LinkedIn feeds. Feel free to reach out to me at LKDIN

To Know more about me, visit my personal webpage @meetakbari.me

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