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A Verilog based Fractal Set Generator for the Xilinx Artix 7

Verilog 35.27% HTML 34.65% Batchfile 0.34% Python 0.01% VHDL 14.08% Shell 4.86% Tcl 6.21% Stata 1.61% SystemVerilog 0.29% C 2.67%
fractal mandelbrot fpga pixel porch vga-driver hsync undergraduate xilinx xilinx-ise

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