Unable to simulate with Verilator: Circular logic error about minerva

[whitequark]

This is an nMigen bug. The problematic lines all are: assign \$verilog_initial_trigger = \$verilog_initial_trigger;, which is a true positive from Verilator's POV. The reason for \$verilog_initial_trigger's existence is that a statement like always @* x = 1; in Verilog will never execute because its implicit event expression list is empty. However, with current Yosys master (specifically, anything that has the proc_prune pass), such pathological statements will never be emitted. (Statements like always @* if(y) x = 1; will be, but these are fine, since a conditional does read something.)

I will fix this as it is quite easy.

[whitequark]

Let me know if this nMigen patch works for you:

diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py
index 8faf58a..eb98a34 100644
--- a/nmigen/back/verilog.py
+++ b/nmigen/back/verilog.py
@@ -39,6 +39,7 @@ def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog
 read_ilang <<rtlil
 {}
 rtlil
+{prune}delete w:$verilog_initial_trigger
 {prune}proc_prune
 proc_init
 proc_arst

[enjoy-digital]

Thanks for the quick answer/patch, simulation is working correctly with it 👍

[whitequark]

m-labs/nmigen@4d6ad28