minerva-cpu / minerva Goto Github PK

m-labs/nmigen@e18385b broke Minerva:

  File ".../litex/soc/cores/cpu/minerva/verilog/minerva/units/decoder.py", line 77, in elaborate
    fmt = Signal(max=Type.J)
TypeError: __init__() got an unexpected keyword argument 'max'

Are you planning to update Minerva to the new nMigen 0.2.dev API or should we stay on nMigen 0.1 for now until a nMigen 0.2 is released?

Hi,
I am not able to successfully run a quick start example.
Could you please suggest what might be wrong.
Thanks.

Environment (Win10):

1. nmigen installed
2. Yosys (yosys-win32-mxebin-0.8.zip) installed
3. Minerva installed
4. Issue #1 bypassed by commenting out missing module import and tap creation in file top.py

Execution log:

C:\Users\anton\OneDrive\Desktop\RISC-V\minerva>python build.py > minerva.v
Traceback (most recent call last):
File "build.py", line 48, in
main()
File "build.py", line 44, in main
print(verilog.convert(frag, name="minerva_cpu", ports=ports))
File "C:\Users\anton\AppData\Local\Programs\Python\Python37-32\lib\site-packages\nmigen\back\verilog.py", line 48, in convert
raise YosysError(error.strip())
nmigen.back.verilog.YosysError: ERROR: Parser error in line 5444: syntax error

When elaborating Minerva with upstream sources and tools (Minerva, nMigen, Yosys), verilator does not seem able to compile the elaborated verilog:

%Error: minerva.v:10300: Wire inputs its own output, creating circular logic (wire x=x)
%Error: minerva.v:10226: Wire inputs its own output, creating circular logic (wire x=x)
%Error: minerva.v:9597: Wire inputs its own output, creating circular logic (wire x=x)

The CPU has been generated with:

python3 cli.py --reset-addr=0 --with-muldiv

Assuming a RISC-V toolchain and Verilator are installed, the error can be reproduced with:

wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
chmod +x litex_setup.py
sudo ./litex_setup.py init install
lxsim --cpu-type=minerva

Here is the elaborated CPU: minerva.zip

I'm missing some basics here for sure, but maybe you can help me find out what I can expect and what to look at.

Situation: I have a small design with minerva, a Wishbone bus that is shared between cpu.ibus and cpu.dbus through a priority arbiter, and some devices on the bus:

• ROM (nmigen-generated) with some bare-metal instructions at the reset vector
• some bytes of SRAM (nmigen-generated)
• a controller that interfaces a 128 MBit NOR flash
• 8 LEDs I can write to and read from at one single address..

JTAG issues, using OpenOCD:

Open On-Chip Debugger 0.10.0+dev-00626-g7eaf60f1b (2019-07-29-16:00)
[...]
Info : BCM2835 GPIO JTAG/SWD bitbang driver
Info : JTAG only mode enabled (specify swclk and swdio gpio to add SWD mode)
Info : RCLK (adaptive clock speed) not supported - fallback to 200 kHz
Info : JTAG tap: minerva.cpu tap/device found: 0x10e31913 (mfg: 0x489 (SiFive, Inc.), part: 0x0e31, ver: 0x1)         
Info : datacount=1 progbufsize=0       
Warn : We won't be able to execute fence instructions on this target. Memory ma
y not always appear consistent. (progbufsize=0, impebreak=0)
Info : Examined RISC-V core; found 32 harts
Info :  hart 0: XLEN=32, misa=0x0
[...]

• after doing halt I can read the registers x1,x2,x3... but reading x32 (PC) always returns 0.
• with the CPU in halted state, doing step fails, though afterwards I can resume manually:

> step
unable to resume hart 0
  dmstatus =0x00020882
  was stepping, halting

• GDB can't attach to my OpenOCD server:

GNU gdb (GDB) 8.3.0.20190516-git
[...]
(gdb) target remote rpi:3333
Remote debugging using rpi:3333
bfd requires xlen 8, but target has xlen 4

Any help understanding these issues is greatly appreciated.

Hi,
It seems some dependencies are missing.
Could you please double check.
Thanks.

Execution log:

C:\Users\anton\OneDrive\Desktop\RISC-V\minerva>python build.py > minerva.v
Traceback (most recent call last):
File "build.py", line 3, in
from minerva.core import Minerva
File "C:\Users\anton\OneDrive\Desktop\RISC-V\minerva\minerva\core.py", line 14, in
from .units.debug import *
File "C:\Users\anton\OneDrive\Desktop\RISC-V\minerva\minerva\units\debug_init_.py", line 1, in
from .top import *
File "C:\Users\anton\OneDrive\Desktop\RISC-V\minerva\minerva\units\debug\top.py", line 4, in
from jtagtap import JTAGTap
ModuleNotFoundError: No module named 'jtagtap'