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microblaze_tutorial

microblaze_zynq

miniblaze

Simple implementation of the microblaze instructions set

minins_cdh_v1.0

This repository is for Zynq embedded codes

model-train-control

ECE 4534 Model Train Control Spartan-3E/Microblaze Code

mpsoc-manifest

Repo manifest files for Mentor Embedded release of Android for Xilinx Zynq UltraScale+ MPSoC

msc_dse_esfpga

FPGA based Embedded Systems module assignment

nanocounter

An FPGA/STM32 based frequency counter with an Android user interface

nexys4ddr

Various projects for the Nexys4DDR board from Digilent

opencl_examples_zedboard

This repository contains a set of examples of opencl code that can run on the zedboard zynq all programmable soc.

otawa-microblaze

plugh-1

A CPU on an FPGA that you can play Zork on

pothos-zynq

DMA source and sink blocks for Xilinx Zynq FPGAs

projects-object_tracking-

object tracking (use Vivado HLS)

qrshls

QRS detection algorithms used with Vivado HLS

sab4z

A simple example design for Zynq-based boards.

serial_processors_project

A repository to track my work on my Final Year University Project to build two bit-serial processors and compare their executions against custom hardware and the MicroBlaze Processor.

sign-forth

forth for MicroBlaze

software

synthos-robot-arm-demo

Multiprocessor Xilinx-controlled robot arm using SynthOS ASOSes for PowerPC and Microblaze.

thesis

This GitHub repository contains all the source code of the ECG Detector developed as part of my Master Thesis project. The VHDL implementation of the ECG Detector as well as the tcl-script to regenerate the Vivado projects can be found in the Vivado folder. The C-source for the ECG Acquisition unit on Arduino and for the ECG Detector's Control Units on ARM are located in the SW folder.

u-boot-digilent-dev

The official Xilinx u-boot repository

u-boot-zynq

vga_1.0

AXI memory-mapped VGA module originally designed for the Avent Zedboard

vga_example

This repository contains a Vivado 2015.3 Project that runs an example application for the VGA_1.0 IP core. Althrough the core had originally been created for the Avnet Zedboard, this example was created for the Digilent Zybo.

vhdl_game

A game written for the Zynq-7000 series FPGA (Zybo board), using an external touchscreen

virtex6-microblaze-lcd

vision-zynq

update

vivado-boards

vivado-kmeans

Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs