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The repository hosts an ongoing project dedicated to the development of an implementation for the Advanced Encryption Standard (AES) 128-bit block cipher in UART communication. Please be advised that this project is currently in progress and subject to updates.

Python 7.29% HTML 72.22% Verilog 19.84% Standard ML 0.02% Scheme 0.01% Stata 0.62%
aes-decryption aes-encryption axi-stream communication communication-protocol cyclic-redundancy-check uart verilog

aes_over_uart's Introduction

AES-128 in UART

The repo contains an implementation of Advanced Encryption Standard 128-bit block cipher in UART for serial communication.

Selection

  • UART for serial communication
  • AXI Stream Interface for UART
  • Encryption for secure transmission
    • AES encryption module
    • AES deception module
  • Cyclic Redundancy Check (CRC-16) for data validation

Encryption Module

Takes 128Bit text input and generate cipher text of the same length

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