Chisel (Constructing Hardware In a Scala Embedded Language) is a hardware construction language embedded in the high-level programming language Scala. Chisel is a library of special class definitions, predefined objects, and usage conventions within Scala, so when you write Chisel you are actually writing a Scala program that constructs a hardware graph. As you gain experience and want to make your code simpler or more reusable, you will find it important to leverage the underlying power of the Scala language. We recommend you consult one of the excellent Scala books to become more expert in Scala programming.
For a tutorial covering both Chisel and Scala, see the online Chisel Bootcamp.
This page serves as a quick introduction to Chisel for those familiar with Verilog. It is by no means a comprehensive guide of everything Chisel can do. Feel free to file an issue with suggestions of things you'd like to see added to this page.
| Verilog | Chisel |
module Foo (
input a,
output b
);
assign b = a;
endmodule |
class Foo extends Module {
val a = IO(Input(Bool()))
val b = IO(Output(Bool()))
b := a
} |
| Verilog | Chisel |
module PassthroughGenerator(
input [width-1:0] in,
output [width-1:0] out
);
parameter width = 8;
assign out = in;
endmodule |
class PassthroughGenerator(width: Int = 8) extends Module {
val in = IO(Input(UInt(width.W)))
val out = IO(Output(UInt(width.W)))
out := in
} |
module ParameterizedWidthAdder(
input [in0Width-1:0] in0,
input [in1Width-1:0] in1,
output [sumWidth-1:0] sum
);
parameter in0Width = 8;
parameter in1Width = 1;
parameter sumWidth = 9;
assign sum = in0 + in1;
endmodule |
class ParameterizedWidthAdder(
in0Width: Int,
in1Width: Int,
sumWidth: Int) extends Module {
val in0 = IO(Input(UInt(in0Width.W)))
val in1 = IO(Input(UInt(in1Width.W)))
val sum = IO(Output(UInt(sumWidth.W)))
// a +& b includes the carry, a + b does not
sum := in0 +& in1
} |
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