myriadrf / xtrx-fpga-source

The source code for the XTRX FPGA image

XTRX SDR FPGA image source code

This repository contains the source code of the XTRX SDR FPGA image.

How to build

You will need a copy of Vivado, which can be freely downloaded on the Xilinx website.

Start by sourceing the settings64.sh file from the Vivado install. For example:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

To build the bitstream, ensure you are in the fpga-source directory and the same shell run:

cd top/xtrxr5
./build.sh

If successful, the output bitstream will be available in the following path:

top/xtrxr5/xtrxr5/xtrxr5.runs/impl_1/xtrxr4_top.bit

Programming with OpenOCD and JTAGHS2 cable

Inside the openocd directory, there are scripts to allow programming with OpenOCD and a Digilent JTAG HS2 cable

After the bistream is built, one may simply run:

./prog.sh

to flash the bitstream to the xtrx device.

License

RTL IP sources are released under the CERN Open Hardware Licence Version 2 - Weakly Reciprocal Please refer to the LICENSE file of the source code for the full text of the license.

xtrx-fpga-source's Issues

Block Diagram for FPGA Source

Hi Guys,

First of all - thanks for sharing.
My engineers tried to work with the code, these are the issues we encountered:

1. After compilation all files, compilation Verilog issues:
   1.1 File qspi_flash.v - include 2 modules : qspi_phy and qspi_flash
   Compilation error as user define output signal with reserve name as follows:
   output reg [3:0] do,
module qspi_phy , I change the name to da and it pass compilation.
   The same with module qspi_flash, I change output do to db
   File ul_qspi_mem_async.v - instantiate qspi_flash , need to change .do to .db
   1.2 module v3_pcie_app.v instantiate blk_mem_gen_nrx - I couldn’t find this module
   1.3 When I tried to make elaboration to the top I failed due to 1.2

2. Simulation Verilog issues: Very important, do you have Test Bench for the top, i.e. tb_xtrxr4_top ?

3. We need the block diagram of the system

Thanks
Tal

@chemeris

onepps_ctrl.v and g_timed_cmd.v sources not included

The onepps_ctrl and g_timed_cmd modules in xtrx_peripherals.v have been disabled by the xtrxr4_top.tcl script but we would potentially like to implement the functionality. The 29 Oct 2020 FPGA source code drop does not include onepps_ctrl.v or g_timed_cmd.v. Are they available?

I have the first XTRX version board. Can the source code used or do I need the PRO version.

I have the first XTRX version board. Can the source code used or do I need the PRO version.

how to use it!

这个玩意怎么玩的？都不知道怎么用