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aes

AES core written in Verilog. Forked from https://git.cryptech.is/cipher/aes.git/

aes-siv

AES-SIV core written in Verilog

alice-lg

Alice - Through the Looking Glass https://lg-beta.de-cix.net https://lg.ecix.net

api_extension

api_extension core written in Verilog. Used by the FPGA_NTP_SERVER project

arouteserver

A tool to automatically build (and test) feature-rich configurations for BGP route servers.

base45

Specification of base45 encoding

client_python

Prometheus instrumentation library for Python applications

cmac

CMAC core written in verilog

cpython

A modified version of Python with support for the SSL_export_keying_material function. This function is neccesary to be able to implement the NTS protocol in Python.

createtables

Creation of tables for IDNA

django-admin-json-export

draft-faltstrom-unicode12

Source for the draft-faltstrom-unicode11 internet draft

fpga_ntp_server

A FPGA implementation of the NTP and NTS protocols

go-cidrman

golang CIDR block management utilities

gobgp

BGP implemented in the Go Programming Language

gobgp_exporter

Prometheus Exporter for GoBGP

ipsec_exporter

Prometheus exporter for IPsec metrics.

keymem

Key memory core written in Verilog. Used by the FPGA_NTP_SERVER project

libaes_siv

An RFC5297-compliant C implementation of AES-SIV

md5

MD5 core written in Verilog

neorv32

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

netbox

IP address management (IPAM) and data center infrastructure management (DCIM) tool.

nixieclock-ncs314

Enhanced software for the GRA & AFCH NIXIE tube clock

nts

NTS core written in Verilog. This is just a core, see the FPGA_NTP_SERVER project for a complete implementation of the NTS protocol in a FPGA.

nts-poc-python

NTS proof of concept in Python

nts_noncegen

Nonce generator core written in Verilog

openvpn-status

Parse OpenVPN status logs in Python

pypeeringmanager

Simple Python client for the Peering-Manager API

robust-tjanst

rosc_entropy

Ring oscillator core written in Verilog. Forked from https://git.cryptech.is/rng/rosc_entropy.git/