- Toast is a RISC-V soft core written in Verilog that implements a subset of the RV32I ISA version 2.2.
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Documentation: https://toast-core.readthedocs.io/en/latest/
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Goals:
- Produce a core that is capable of running the RV32ui unit tests from official riscv-tests repo
- Gain familiarity with open-source tools
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Stretch Goals:
- Memory-mapped I/O and UART peripheral
- Zicsr extension support
- ISR handling
- UVM and/or Formal Verification
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Toast currently is capable of passing all RV32ui unit tests and has passed post-synthesis timing at 100MHz targeting Xilinx Artix-7 FPGA.
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Has not been tested on hardware until updated here. Very much still WIP, however updates may be infrequent due to school and other commitments.
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Toast does not support interrupt handling, nor the CSR, FENCE, EBREAK, or ECALL instructions.
Makefile
Run make alltests
to compile, link and convert riscv-tests to hex memory files and run the entire battery of tests.
Run make alltest_vcd
to run all tests and generate a vcd file.
Memory generation requires a 32-bit riscv-unknown-elf toolchain installed at /opt/riscv32i, as well as elf2hex. Testbench is ran using Icarus Verilog. See the Makefile targets for more details.
/docs
- Contains datapath diagrams and notes, wip
/scripts
- Contains shell scripts to compile, link, and generate memory files from the riscv-tests, as well as a script to run tests and dump vcd from vivado
/rtl
- Contains all source files for Toastcore and UART peripheral (WIP)
/test
- Contains the riscv-tests, testbench, and GTKwave translate filter files/processes