nitcloud / digital-ide Goto Github PK

i meet some problem like this
Using Python within TCL script in Vivado 2019.1

I wonder if I need to use python2?
(But when I tried to use python 2.7.5, I met some other problem)

I will add screenshot and log later.

Hello,

First of all, congrats for your work. I think you had a very good idea to combine FPGA development languages support in one extension.

I am running VS Code 1.45.1.
When hoovering the code (.sv, .v), the following error is printed to console:

[2020-05-15 11:59:28.926] [renderer1] [error] An unknown error occurred. Please consult the log for more details.
[2020-05-15 11:59:28.927] [renderer1] [error] Cannot read property 'uri' of undefined: TypeError: Cannot read property 'uri' of undefined at c:\Users\userx.vscode\extensions\sterben.fpga-support-0.1.10\src.Providers\providers\HoverProvider.js:13:67 at processTicksAndRejections (internal/process/task_queues.js:85:5)

如题，但是可以在命令行里用Python操作，下载插件地址在C盘的默认的.vscod里.vscode\extensions\sterben.fpga-support-0.1.10\src.TOOL.Script\start.py

I've installed this plug-in together with several plug-ins which appear in your thanks list and wondering whether this plug-in covers all functions of them (thus I can unistall those plugins).

In https://github.com/Bestduan/fpga_support_plug#thanks:

Thanks

• VHDL
• Verilog_Testbench
• TCL Language Support
• Verilog HDL / SystemVerilog
• SystemVerilog - Language Support

• Issue Type: Performance
• Extension Name: fpga-support
• Extension Version: 0.1.15
• OS Version: Windows_NT x64 10.0.19042
• VS Code version: 1.57.0

⚠️ Make sure to attach this file from your home-directory:
⚠️c:\Users\DELL\AppData\Local\Temp\sterben.fpga-support-unresponsive.cpuprofile.txt

Find more details here: https://github.com/microsoft/vscode/wiki/Explain-extension-causes-high-cpu-load

• Issue Type: Performance
• Extension Name: fpga-support
• Extension Version: 0.1.15
• OS Version: Windows_NT x64 10.0.22000
• VS Code version: 1.59.0-insider

Find more details here: https://github.com/microsoft/vscode/wiki/Explain-extension-causes-high-cpu-load

安装本插件后无法在vscode中simulate，已安装iverilog且path环境变量已设置，可于powershell中使用iverilog -o指令编译成功。
但使用本插件在vscode的.v文件界面右键选择Simulate编译时vscode提示如下错误：
'C:/iverilog/biniverilog.exe' �����ڲ����ⲿ���Ҳ���ǿ����еij��� ���������ļ���
来源：FPGA Develop Support（扩展）
注：错误信息实际显示即为乱码

其中，vscode的seetings.json相关设置如下：
"HDL.linting.linter": "iverilog",
"verilog.runInTerminal": true,
"HDL.linting.iverilog.arguments": "-i",
"TOOL.iVerilog.install.path": "C:/iverilog/bin",
"TOOL.gtkwave.install.path": "C:/iverilog/gtkwave/bin",

相应的，系统变量Path如下：
C:\iverilog\gtkwave\bin
C:\iverilog\bin\

我安装的iverilog链接为“http://bleyer.org/icarus/iverilog-v11-20210204-x64_setup.exe”
操作系统为Win10专业版-20H2,操作系统内部版本 19042.1052,处理器为amd 3700x,

所Simulate的文件内容为下述内容，文件编码为UTF-8.

module v1 (
input clock
);
always @(clock) begin
$display("Hello World!");
end

endmodule

I've installed Digital IDE plugin in VSC, windows 10, and tried to generate project.

有的模块例化的时候，port列表总是会出现一些错误，有些port还重复出现，括号也莫名奇妙多，一些内部的reg也在这里显示。

• Issue Type: Bug
• Extension Name: fpga-support
• Extension Version: 0.1.13
• OS Version: Windows_NT x64 10.0.19042
• VS Code version: 1.55.2

⚠️ We have written the needed data into your clipboard. Please paste! ⚠️

simulation后会报一个警告，然后gtkwave不弹出

只能手动打开

Platform

Ubuntu20.04.1 LTS X86_64, 5.8.0-59-generic kernel version
Vivado 2020.2, Vitis_HLS 2020.2
Python 3.8.10 runs in GCC 9.4.0

Description

Sytax highlight works fine, but no syntax checking or other features from Xilinx development tool after I set up xilinx install path. It is not fixed even if I changed the software version to 2020.3. Neither vivado or xsct command is valid. I found no answers in closed or opened issue, any suggestion is helpful, thanks!

settings.json
{
    "terminal.integrated.tabs.enabled": true,
    "explorer.confirmDelete": false,
    "TOOL.xilinx.install.path": "/opt/Xilinx/Vivado/2020.2/bin, /opt/Xilinx/Vitis_HLS/2020.2/bin, /opt/Xilinx/Vitis/2020.3/bin"
}

如图，我将UART_Decode这个文件改名字为UART_Decode_Debug，结果修改前的文件名字也保存下来了，实际上文件夹里没有UART_Decode这个文件了

如题，我在RTL文件中引用了宏定义文件：

`include "defines.v"

该文件存放了形如

 `define     RstEnable       1'b1        //复位信号有效
 `define     RstDisable      1'b0        //复位信号无效

的宏定义。

此时在顶层文件右键点击simulate，会出现找不到宏定义文件的错误：

ERROR From iverilog : c:/Users/Desktop/mips_cpu/pc_reg.v:2: Include file defines.v not found

请问是否可以在iverilog编译命令中添加-I includedir选项以指定verilog中include指令的搜索路径呢？

在设置好配置文件之后，仍按照默认模板生成vivado工程。
我在如下位置设置了配置文件：
./property.json,./.vscode/property.json,prjInitParam.json
文件内容：

{
	"FPGA_VERSION": "xilinx",
	"PRJ_NAME": {
		"FPGA": "mipscpu"
	},
	"SOC_MODE": {
		"soc": "none"
	},
	"enableShowlog": true,
	"Device": "none"
}

发现工程名称均为默认的template.
检查启动脚本Run.tcl，发现脚本读取了.vscode\extensions\sterben.fpga-support-0.1.16\resources\tool目录下的CONFIG文件。而此文件在创建配置文件时并未被修改。

set soc           none
set Device        none
set prj_name      template
set enableShowlog false
set fp [open $root_path/CONFIG r]
while { [gets $fp data] >= 0 } {
	if { [string equal -length 13 $data "PRJ_NAME.FPGA"] == 1 } {
		gets $fp prj_name
		if {$prj_name == "undefined"} {
			set prj_name template
		}
	}
...

使用例化功能进行模块例化时，最后一个信号末尾有逗号，导致语法错误。

pc_reg u_pc_reg(
	//ports
	.clk 		( clk 		),
	.rst 		( rst 		),
	.pc  		( pc  		),
	.ce  		( rom_ce_o  ),
);

我新建了一个src的文件夹，然后放进去一些verilog文件，点击vscode左侧

然后就会报

这种错误，然后我想着是不是没建立工程，然后按F1生成一个property文件，还是不行

请问可以添加与Verilog一样，对SystemVerilog的语法支持嘛

上次更新后能自动打开gtkwave了，但是自动补全又不工作了

Just as a suggestion, but you might want to include an English version of the main README.md file. It might help increase the number of user installs the extension gets in VS Code.

Likewise, having the CHANGELOG.md contain the project revision information might be something worth looking into.

Here's my shot at the translation and changelog (rename to remove the *.txt extension):

• README.md.txt
• CHANGELOG.md.txt

不知道为什么input和output不能正常高亮

我之前一直用的Verilog-HDL/SystemVerilog/Bluespec SystemVerilog插件，但是vscode一次更新后，我的自动补全就不能补全自己输入的变量

不知道这两个bug之间有没有联系。

Is it possible to refactor a signal/port name present in multiple modules (files: *.v)?

插件版本：0.2.1
现象：
使用vivado作为vlog Linter时功能失效，不再标识语法错误。vivado版本为2021.2，路径如图所示

使用modelsim作为Linter则正常。
使用iverilog作为vlog Linter时，iverilog不支持systemverilog语法。

testbench里不支持使用defparam关键字修改模块里的parameter，使用defparam会报错找不到该参数。请问这个问题怎么解决？

效果类似于：

光标停在begin处会自动框起来end，反过来也是可以的

项目文件结构如图

刚刚写一点testbench的时钟

爆栈 然后 file部分不显示

不知道是不是我写的外部定义的parameter不规范，左边FILE找不到文件。

• Issue Type: Performance
• Extension Name: fpga-support
• Extension Version: 0.2.3
• OS Version: Darwin x64 21.3.0
• VS Code version: 1.67.0

⚠️ Make sure to attach this file from your home-directory:
⚠️file:///var/folders/2w/tcrghhpj2n56nhpmj67hjk5r0000gn/T/sterben.fpga-support-unresponsive.cpuprofile.txt

Find more details here: https://github.com/microsoft/vscode/wiki/Explain-extension-causes-high-cpu-load

使用generate for语句进行模块的批量例化时，模块之间的引用层次关系没有在FLIE中显示。

先贴一下具体环境：

VSCode：

• 版本: 1.66.2 (user setup)
• 日期: 2022-04-11T07:46:01.075Z
• Electron: 17.2.0
• Chromium: 98.0.4758.109
• Node.js: 16.13.0
• V8: 9.8.177.11-electron.0
• OS: Windows_NT x64 10.0.19044

Digital IDE：
v0.1.22

情况描述：
在.v源码文件视图右键菜单点击"show FSMGraph"后能正确打开状态机预览图的窗口，也能正确绘制状态转换图，同时也能正确识别我的大写“STATE”的状态寄存器定义，点击状态机中各个节点也能在源码视图跳转到正确语句块。但是在状态图预览窗口点击顶部按钮“Save as SVG”时无反应，按钮卡死在按下状态，没有弹出保存对话框等动作，就是单纯地没有反应了。
无报错、无输出，找不到相关的日志记录等。

备注：
我使用这个插件进行开发的时候，开发的不是Xilinx的项目，而是国产安路科技的，语言是Verilog，但没有安装Xilinx，Iverilog等环境，但安装并配置了ModelSim的目录。

Issue Type: Bug

This extension causes high CPU utilization.

Extension version: 0.1.15
VS Code version: Code 1.55.2 (3c4e3df9e89829dce27b7b5c24508306b151f30d, 2021-04-13T09:35:57.887Z)
OS version: Windows_NT x64 10.0.19042

vsliv368:30146709
vsreu685:30147344
python383:30185418
pythonvspyt700cf:30270857
pythonvspyt602:30294772
vspor879:30202332
vspor708:30202333
vspor363:30204092
vstes627:30244334
pythonvspyt639:30291489
pythontb:30283811
vspre833cf:30267465
pythonptprofiler:30281270
vshan820:30294714
pythondataviewer:30285071
vscus158:30286553
vscgsv2ct:30294353

Description

I tried using pyperclip to copy instance to clipboard, and succeeded in macOS.

I am not sure if it makes sense on other os. I will try it later.

Environment

• OS: macOS 10.15.4
• Python: 3.7.7

Solution

Import the module:

import pyperclip

Use a string to record data, for example, instance_data.
And then just use

pyperclip.copy(instance_data)

to copy the string to clipboard.

• Issue Type: Performance
• Extension Name: fpga-support
• Extension Version: 0.1.15
• OS Version: Windows_NT x64 10.0.19042
• VS Code version: 1.56.2

⚠️ Make sure to attach this file from your home-directory:
⚠️c:\Users\ADMINI~1\AppData\Local\Temp\sterben.fpga-support-unresponsive.cpuprofile.txt

Find more details here: https://github.com/microsoft/vscode/wiki/Explain-extension-causes-high-cpu-load

如图

The foreach command is not defined in TCL syntax definition file. Therefore, the for part is highlighted and the remaining each part is left unattended.

使用iverilog在线仿真报错：找不到gtkwave；
但是我已经将gtkwave加入到系统环境变量,并且我在终端可以直接打开gtkwave:

Extension does not work in this project:

In other projects, the extension works fine

使用版本0.2.4
当前启用扩展：

扩展设置：


环境变量也已设置

但不会报错

但启用Verilog-HDL/SystemVerilog/Bluespec SystemVerilog 这个扩展之后，该扩展的语法检查功能成功报错

请问一下，为什么我点击了却没有任何反应呢

按了几个插件之后就突然不行了，现在将之前的无关插件都卸载了，也不行

你好，请问可不可以出一个教学视频或者完整的配置教程呀，有很多东西看不明白。

比方说我的vivado 2019.2下面就没有SDK目录。

I used vscode bisect to identify the error. Each time at startup of vscode, it kills my extension host.

综合testbench报错：
ERROR: syntax error, unexpected '#'

综合调用的模块则成功

在 FPGA Options 中 Launch 时 ，使用了命令

vivado -mode tcl -s c:/Users/XXX/.vscode/extensions/sterben.fpga-support-0.1.21/resources/script/xilinx/launch.tcl -notrace -nolog -nojournal

但是本文件找不到，即报错

couldn't read file "c:/Users/XXX/.vscode/extensions/sterben.fpga-support-0.1.21/resources/script/xilinx/launch.tcl": no such file or directory

，经查阅 git 仓库相应位置也没有这个文件，而这个文件可能是在 git 仓库的
/resources/script/xilinx/soft/launch.tcl下的同名文件，疑似版本更新时脚本未更新

网站bestduan.github.io是作者自己停了还是故障了？

文件栏里中，层次树的子模块及其分支不再显示，如图：

文件位置如图，所有文件都在工作区文件夹下：

If we have an existing project, 'startFPGA' seems to run 'Run.tcl' by:

source ${HOME}/.vscode/extensions/sterben.fpga-support-0.1.10/src/.TOOL/Xilinx/Script/Xilinx_TCL/Vivado/run.tcl

We can execute it successfuly on Windows since Windows is case insensitive.
But Linux is case sensitive, so it cannot find file "run.tcl".

This problem can be easily solved by modifying the line in file:
${HOME}/.vscode/extensions/sterben.fpga-support-0.1.10/src/.TOOL/.Script/start.py