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Easy tools for all designs

VHDL 73.20% Verilog 15.77% Stata 1.78% Tcl 9.25%

fpga_tools's Introduction

FPGA_tools

Easy tools for all designs

async_preset - form strobe for one clk period after the appearance of an asynchronous signal at the input port.

cdc_pulse - module to clock domain crossing single pulse with measured frequency of domains.

complex_multiplier - pipline module multiply two complex numbers with small device area.

debouncer - module for eliminating bounce of input ports.

front_detector - generate pulse to changed edge type.

strobe_gen - generate single pulse with user's start and duration after start clk.

functions - package with often used functions.

sort - module for growing sort pipeline input values with clock domain crossing.

window analysis - module for calculate mean value, max value and index of max value. See readme file inside folder before use

tcl - set of scripts for automation design and verificate FPGA modules

make_project - script for create, synthesis and implementation Vivado project from given sources

template.vhd - universal template file for new .vhd modules

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