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We have to make sure that our programs run on CEAT computers. Things to check 
for:

- Does it allow installation?
- Does it allow execution of exe files?
- Does it have Java Runtime Environment installed?
- Can the serial port be used?

this is just to identify any obvious bugs before we start adding all of the 
forwarding logic.

A decision was made to move the branch/jump logic into the EX stage (from the 
ID stage). The diagram has been updated to reflect this, and the HDL needs to 
be changed as well.

Additionally, the register file needs to be updated to write on the negative 
edge.

See summary.

see summary

We have the old user manual as a google doc. It needs to be partitioned into 
the wiki. There are some parts that will stay in the "user manual" section, 
others will go into the development section.

see summary.

See summary. Make sure forwarding and stalling work too.

Create your profile page

Since this has become a more academic project, I'm wondering if it makes sense 
to keep this site Vanilla, while having student sections create their own 
google code site (or we'll create one for them). We could then just link to 
theirs from here.

The simulation core doesn't prepend the jump destination with the most 
significant 4-bits of the PC.

The plp metafile has extra "stuff" in it, and it not readable:

^@P^@L^@P^@-^@2^@.^@0^@
^@D^@I^@R^@T^@Y^@=^@1^@
^@
^@f^@l^@o^@a^@d^@.^@a^@s^@m^@

should be:

PLP-2.0
DIRTY=1

fload.asm

What steps will reproduce the problem?
1. Start a computer architecture education platform
2. Create google code website
3. ???

What is the expected output? What do you see instead?
We expect to see a kickass platform. But we see nothing.

Please use labels and text to provide additional information.

Get the 1.0 source tree, minus some of the modules like the vga module building 
with the new block ram system and build script. 

This will be the working code to update the rest of the system on, starting 
with the new cpu core, then memories, building new modules, and updating old 
modules.

Need a memory module for the new board, with instruction and data ports. This 
is actually two parts:

1. The memory module wrapper that will eventually instantiate the cache and 
main memory modules.
2. The main memory module (the caches will come in a later ticket).

Can't find the drivers...

We need this in the source tree, and it needs to be linked in the "about" 
dialog in the program.

branch resolution needs to take place in the ID stage. see page 377 in H&P book.

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if an assembly file ends with a comment line, the assembler fails.

1. Create a mercurial tutorial wiki page on this site, with specifics about 
this project (ie students should only commit to the student branch, etc)

2. Create a mercurial certification. This can be done via a quiz made through 
google docs, via the google plp account.

Create a python script to autogenerate the plp rom module from the plp.hex file 
in a plp project. 

The intent is to compile the fload bootloader and build the rom module from 
that. The hdl build script could invoke this, or it could just be used when 
needed.

in ID stage, jump address calculation for j and jal is broken. It needs to be 
shifted and concatenated with upper bits of PC.

well?

We need a proper port of CVER to Win32, without using Cygwin.

We can host that here once it's compiled and packaged.

Assigning this to BG.

Some control logic is broken due to confusion with the opcode and function 
fields. 

In particular the jal and jr instructions are broken.

see summary. 

This is the most annoying thing ever. If there were a priority higher than 
high, that's where I would put it.

.

I have a link in the main portal for this. 

see summary

put this on pumpkin. both the source and wiki repos.

Needed so I can create the programmer and begin testing the new hardware.

see summary

see summary

see summary

See summary.

See summary.

Summary says it all

the plp file format contains no information about the org data in programs, 
making it *impossible* to program the board.

The likely solution is to add an org address to the metafile.

jal and jalr don't actually write the link register.

the programmer code has the address 0x00000000 hardcoded, it needs to use the 
org data in the metafile or whereever it ends up.

Summary says it all.

lw sw combinations will forward correctly for the following sequence:

lw $t0, 0($t1)
sw $t0, 0($t2)

That's fine, but the forward override logic ignores the rs field when a store 
word is present:

lw $t0, 0($t1)
sw $t2, 0($t0)

Will incorrectly assume a forward.

http://code.google.com/p/progressive-learning-platform/wiki/UserManual#Tools

Needs to be updated with all of the usage information about PLPTool. This 
probably can't happen until the GUI is finished.

Screenshots will be nice here too. This will be the official manual/tutorial.

see summary

Most of the modules should stay the same, but perhaps just need to be cleaned 
up.

The VGA module needs to be updated with an inferred ram.
The UART may have an endian issue that needs to be looked into.

full description is in summary.

Can be reproduced by using the .asciiz token, which generates:


[E] #16 PLPAsm(fload.asm): Unable to process token .asciiz in line 13

update the file format to support multi-org statements.

Method programWithAsm in the serial programmer class seems to be a pointless 
method. Shouldn't we always use the programWithPLPFile method? 

I'm thinking that the workflow would be to assemble, which creates a PLP file, 
and then program with that file. If there's a good reason to keep this method, 
then we should change it so that we don't have so much duplicate code (i.e. 
have those methods extract the object code and then call a common program 
method).