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In snap/snap_env.sh, user specifies a path to ibm.com_CAPI_PSL9_WRAP_2.00.zip file and assign it to PSL9_IP_CORE variable.
In psl/Makefile, the zip file is searched in current snap path regardless of the PSL9_IP_CORE path!
Thus it is impossible to specify a path to a zip file which is not in the current snap path.

From the capi-bsp directory (latest release), when executing for example:

make clean
make AD9V3

we get the following error if and only if we use vivado 2018.3

.../...
Generating capi_bsp IP
Applying patches
Creating capi_bsp IP container
ERROR: [filemgmt 56-196] The vivado project is inside the IP directory. You can not convert this IP to a core container.
make[1]: *** [/afs/vlsilab.boeblingen.ibm.com/proj/fpga/framework/mesnet/snap_test_hlsmk/hardware/capi2-bsp/AD9V3/.create_ip_done] Error 1

Error is located at this line
which is known and referenced by Xilinx here

Adding the following line in common/tcl/create_capi_bsp.tcl should implement this workaround
set_property coreContainer.enable 1 [current_project]
The problem is to find where to implement that

On the N250S+ in a Zaius P9 system, the card reset via sudo sh -c "echo 1 > /sys/class/cxl/card0/reset"doesn't work most times. This means the card can't be updated reliably without power cycling the system, and automated Jenkins testing is not possible.
This may also affect other CAPI 2.0 cards on P9, so the fix must be done for all supported cards.

The issue was found and fixed in another N250SP design:
Changes required for CAPI2-BSP/N250SP/src/capi_bsp.vhdl: It is missing some fixes related to reset that might be causing lab issues.

1. The MCM that generates the psl_clk and icap_clk should have its reset input tied off:
   -- MMCM to generate PSL clock (100...250MHz)
   pll0: flashgtp_clk_wiz
   PORT MAP (
   clk_in1 => pcihip0_psl_clk, -- Driven by PCIHIP
   clk_out1 => psl_clk, -- Goes to PSL logic
   clk_out2 => psl_clk_div2, -- Goes to PSL logic
   clk_out3 => icap_clk, -- Goes to SEM, multiboot
   clk_out3_ce => icap_clk_ce, -- gate off while unstable to prevent SEM errors
   -- reset => pcihip0_psl_rst, -- Driven by PCIHIP
   -- reset was pcihip0_psl_rst. this killed the clock to icap before a reconfig could complete
   reset => '0',
   locked => clk_wiz_2_locked
   );

2. The reset inputs to PSL9_WRAP_0 need to change as well:

   -- PSL_RST and PCIHIP_PSL_RST must both be asserted if one is asserted
   -- If only 1 is asserted, async fifo gets into invalid state
   PSL_RST         => pcihip0_psl_rst,  -- was psl_reset_sig,
   PSL_CLK         => psl_clk,
   PCIHIP_PSL_RST  => pcihip0_psl_rst,
   PCIHIP_PSL_CLK  => pcihip0_psl_clk
   

=> take over latest PSL changes into capi2-bsp, in addition to the two changes listed above