panda-cores / pandazero

A pipelined, in-order implementation of the RV32I ISA

PandaZero

A RISC-V processor, destined to become a microcontroller!

Quick overview:

• RV32I ISA
• 5 Stage Pipeline
• 1kB L1 instruction cache
• 1kB L1 data cache (write back)
• Simple branch predictor (predict backward branches as taken)
• Pipeline hazard detection & mitigation by HW via pipeline stalls
• Core connected to wishbone bus
• Debug module (not consistent with RV spec for debug modules, but supports extensive testing)
• 1x Timer
• 8x GPIO

Upcoming features/improvements (in order of priority):

• Exception raising on illegal instruction
• Making debug module consistent with RV spec
• Extension to RV32F ISA (floating point)

pandazero's Issues

Execute 10 random programs successful on core

Execute 10 random programs successful on core (to find errors)

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AUIPC, JALR, JAL not correct

The above instructions only trigger a jump to the respective address, but the flush happens immediately and thus it is no longer propagated to the other stages. As a result, the PC+4 is not stored and return is not possible.

Add wishbone to IF & MEM stages

Make the IF and MEM stages wishbone masters to enable usage of a wishbone interconnect, which in turn enables memory mapped peripherals

ttest

Upgrade Wishbone

common repo has new wishbone interfaces, upgrade time!

upgrade debug module

Common is in progress of changing the debug module, upgrade when done

Multiply doesn't work

Investigate whether this is a compiler issue or not

Create debug module

Write a debug module to enable easier testing than looking at the waveforms