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1.0 1.0 0.0 171.09 MB

Verilog 7.59% SystemVerilog 39.65% Shell 12.16% Stata 0.55% Forth 0.12% Tcl 12.70% JavaScript 19.16% Batchfile 0.48% Coq 3.71% VHDL 3.85% Pascal 0.02%

ece540_proj_03's Introduction

Set top level:
- nexys4fpga_v2:         for max frequency = 275MHz, 16 operands
- nexys4fpga_max_inputs: for max frequency = 110MHz, 1024 operands

Strategies:
- synthesis     : the default given by the original deliverable (bestone)
- implementation: the default given by the original deliverable (best_so_far)

ece540_proj_03's People

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Ujjawal Aggarwal avatar

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