HDL SEC/DED Producer
MATLAB/Octave generator of Hamming ECC coder/decoder. Output format is Verilog HDL. Optional adding atop Hamming Coding extra parity bit we have a Single Error Correction/Double Error Detection (SEC/DED) algorithm.
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Russian description available here: http://idoka.ru/verilog-secded-generator/ |
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Now available online version of generator http://idoka.ru/verilog-ecc-generator/ |
Synopsis
Getting Started
Prerequisites
You need installed on your host:
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MatLab
or
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GNU Octave
The GNU Octave required additional toolboxes, under RHEL/CentOS 6/7 systems please type for installs required prerequisites:
$ sudo yum install -y octave-devel
$ octave
octave:> pkg install -forge control
octave:> pkg install -forge signal
octave:> pkg install -forge -verbose communications
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for control package installing Octave version should be >= 3.6.0 |
Installing
Not needed to install
Usage
Just type (by default run matlab target):
make
or if you can forcibly specify target (if you decide which tool will be use):
make matlab
or
make octave
Naming conventions and Integrators guide
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(2m-1, 2m-m-1, 3) - for standard Hamming codes
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(2m, 2m-m-1, 4) - for SED/DED codes
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Using template (n,k,d) where is:
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n = d + k + m; where:
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m - extracted from Hammgen() function, in fact this is width of correction bits
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k - user data width (which should be under ECC protection)
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d = 3 + SECDED_parity_bit_if_used; where 3 - is Hamming distance
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HammingCoder_n_k_d()
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HammingDecoder_n_k_d()
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e.g.:
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..72_64_4
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..71_64_3
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..39_32_4
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..38_32_3
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..26_20_4
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..25_20_3
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HammingCode_kbit.v
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e.g.:
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HammingCode_20bit.v
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HammingCode_64bit.v
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etc..
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ToDo
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Verilog module naming according to the data width
Contributors
Please read CONTRIBUTING.adoc for details on our code of conduct, and the process for submitting pull requests to us.
License
This project is licensed under the MIT License - see the LICENSE file for details
References
Feel free to send me comments, suggestions and bug reports