quartiq / banker Goto Github PK

Hardware

https://github.com/sinara-hw/Banker/wiki

High level description

• 128 digital IO
• fast, batched, synchronous atomic update and sampling
• 400 ns for one bank (16 pins) update rate, 600 ns sustained.
• compact single-port, single SPI bus EEM interface

Implementation steps

• I2C driver for I2C-to-SPI chip and flash memory, flash read, write, verify, erase, restart over I2C
• migen board support
• build scripts
• 4 wire SPI slave
• 7 bit register address space, 16 bit register width, 24 bit SPI transfers
• banked GPIO registers each overing 16 IO (4x2x8 IDC, 4x2x8 VHDCI)
• each with input, output, set, clear register functionality
• atomic synchronous and batched change of arbitrary outputs on CS_N deassert
• clocked only by SPI clock and CS, ensuring minimal input and output jitter
• sampling of inputs on CS assert
• configuration: warmboot, boot bank select, cfg reload, reset, led, drv_oen
• status: cbsel pins, DIP switches, SPI lines
• identification: register with hw version and gw version
• artiq support
• artiq driver documentation
• extend to downstream EEMs (limited by the static ICE40 LVDS direction)

Future

• pulse counting
• configurable high-resolution mapping of pins to EEM0_[4-7]
• unittests

Status: This code is available for funding.

Use a link design similar to Fastino to achieve 1.5 Gb/s and about 112 ns output update interval for each pin.