qz701731tby / mips-pipeline-cpu-with-vga-char-display

Using Verilog and based on vivado, I design a 5-level pipeline CPU and a VGA module to display the information of CPU.

MIPS-pipeline-CPU-with-VGA-char-display

In this repository, I design a 5-level pipeline CPU and a VGA module to display the information of CPU.

Our pipepline realize 24 MIPS instructions (including add、subu、slt、sltu、and、or、xor、nor、sll、srl、sra、addiu、lui、lw、sw、beq、bne、jal、jr、multu、j、ori、addi、add) and are able to run fabonacci, the test file of fabonacci is included in the CPU file.

You can call the VGA IP core directly in the CPU project.