ravencus / multifpga Goto Github PK

Document Aurora clock settings for all three clocks.

1. Definition.
2. Configuration.
3. Usage.

Should include examples.

Generate bitstream for rx_on_demand module and tx_on_demand module using the .tcl and .xsa files under Vivado directory.

This issue is for the purpose of exploring the portability and methods of collaboration with respect to Vivado workflow.

By providing documented procedures for reproducing the demo, this issue should be considered equal workload to the original implementation.

Primary task for Stage One. Implement and test the SFP+ interface on the ZCU102 board.
The section should enable direct BRAM to BRAM transfer, controlled by either PL or PS.
Then formalize it as a memory kernel module in HLS for further design.
Aurora IP should be a good starting point.

Leverage the implemented Tx-Rx module to support on-demand data transfer between two(or more) boards.

• Implement direct PL-to-PL data transfer module with simple protocol for locating target BRAM.
• Remove DMA module.
• On-board test and performance evaluation.
• Stress test.
• Implement Duplex Mode.

Channels should remain open through out the test.

Change the count of sync header 7777 to 3 instead of 4 in both tx_on_demand and rx_on_damand will result in error. This issue aims to figure out the exact data transfer paradigm (i.e. bus width, burst mode, side-channel, framing/streaming, flow control, ...) of the transfer interface.

Suggested workflow:

1. Enable side channel transfer in simulation.
2. Implement transfer with side channel in Vivado and generate bitstream.
3. Research on Framing and Streaming method, as well as their flow control.
4. Implement frame generator for data transfer.
5. Frame checking method.