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Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)

License: Other

C 92.35% Makefile 1.95% Assembly 5.69%

boom-attacks's Issues

Errors Implementing Hybrid Branch Predictors on RISCV BOOM core

I am working on implementing hybrid branch predictors listed below

  • Gshare + TAGE
  • TAGE + Alpha
  • Perceptron + TAGE
  • Gshare + Alpha
  • Perceptron + Gshare
  • Perceptron + Alpha
  • Perceptron + TAGE + Alpha
    I created a class definition of the hybrid predictor in the config-mixins.scala file and create a class instance in the BOOMConfigs.scala file.
    When I try doing that, the results I get are the same as if I run the benchmark programs (multiplication.riscv, qsort.riscv, and dhrystone.riscv) without any branch predictor.

These are screenshots of what I did for the Gshare + TAGE hybrid combination.

The idea is to replace tagless base predictor (PC indexed 2-bit counter bimodal table) of TAGE with Gshare

Class Definition of Hybrid combination of Gshare and Tage in config-mixins.scala file
image

Class instance of Hybrid combination of Gshare and Tage in BOOMConfigs.scala file
image

The CPI I get for all three benchmark programs (multiplication.riscv, qsort.riscv, and dhrystone.riscv) with this hybrid combination is the same as the CPI for when I run the same benchmark programs with no branch predictor.

Status of attacks on chipyard-based boom

I was able to successfully run the conditional branch mispredict and the indirect branch mispredict attacks with this chipyard version and the MediumBoomConfig:
ef404ef0ba6c471430120f13818cc5027225d877

However the return stack buffer attack did not recover the correct secret.

Help..I can't reproduce conditonal branch attack on boom-core in chipyard

my chipyard version is f387c4b99424e869235f927aebcb7dabc643a6f5
and I use CONFIG=LargeBoomConfig or CONFIG=MediumBoomConfig to make verilator and vcs simulator , but using the both two to simulate is not work:

./simulator-chipyard-MediumBoomConfig ~/proj/boom-attacks/bin/condBranchMispred.riscv
This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.
Listening on port 44557
[UART] UART0 is here (stdin/stdout).
m[0x0x80002750] = want(!) =?= guess(hits,dec,char) 1.(9, 33, !) 2.(1, 1, �)
m[0x0x80002751] = want(") =?= guess(hits,dec,char) 1.(1, 1, �) 2.(1, 2, �)
m[0x0x80002752] = want(#) =?= guess(hits,dec,char) 1.(1, 1, �) 2.(1, 2, �)
m[0x0x80002753] = want(T) =?= guess(hits,dec,char) 1.(1, 1, �) 2.(1, 2, �)
m[0x0x80002754] = want(h) =?= guess(hits,dec,char) 1.(1, 1, �) 2.(1, 2, �)
m[0x0x80002755] = want(i) =?= guess(hits,dec,char) 1.(1, 1, �) 2.(1, 2, �)
m[0x0x80002756] = want(s) =?= guess(hits,dec,char) 1.(1, 1, �) 2.(1, 2, �)
m[0x0x80002757] = want(I) =?= guess(hits,dec,char) 1.(1, 1, �) 2.(1, 2, �)
m[0x0x80002758] = want(s) =?= guess(hits,dec,char) 1.(1, 1, �) 2.(1, 2, �)

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