rolandbernard / kleine-riscv

A small and simple rv32i core written in Verilog

Hi there 👋 · My name is Roland Bernard

Nothing more to see here.

kleine-riscv's Issues

Simulation question

When I directly run the make command after git this repo, here I got an error

make[1]: Entering directory '/work/kleine-riscv/tests'
Building build/misc/ackermann
clang-10: warning: argument unused during compilation: '-fuse-ld=lld' [-Wunused-command-line-argument]
error: unable to create target: 'No available targets are compatible with triple "riscv32-unknown-unknown"'
1 error generated.
make[1]: *** [makefile:35: build/misc/ackermann] Error 1
make[1]: Leaving directory '/work/kleine-riscv/tests'
make: *** [makefile:46: tests/build] Error 2

Do you have any suggestion to solve this?

make sim can run correctly.