Name: Rachit Garg
Type: User
Company: ETAS GmbH
Bio: A Solution Engineer specialising in Embedded Systems Engineering.
Setting the right bits at right places 😉.
Exploring Automotive Software, Linux, Rust, C++
Location: Stuttgart, Germany
Blog: rstartech.blogspot.com
Rachit Garg's Projects
Some RISC-V code I tested on Venus Emulator (https://venus.kvakil.me/)
Design of RISC V Processor
Contains code in Rust language using the official book and my own experiments. Book can be found here https://doc.rust-lang.org/stable/book/
Projects built on Rust using gtk4-rs. https://gtk-rs.org/gtk4-rs/stable/latest/book/
Code from the tutorial at https://rust-lang.github.io/async-book/ (Sometimes with additional modifications)
Code from the tutorial at https://rust-cli.github.io/book/index.html
Examples of Design Patterns in Rust inspired from https://rust-unofficial.github.io/patterns/
This repo contains my solutions to the Rustlings exercises. For more info check out : https://github.com/rust-lang/rustlings
Server Designing in C
Projects made using Slint UI Framework in Rust
Example of C++ code to demonstrate SOLID Principles.
Code taken from https://docs.swift.org/swift-book/GuidedTour/GuidedTour.html. Should run
This is going to contain some SysML v2 code. (Work in progress)
The latest monthly incremental release of SysML v2. Start here.
Source code for the C++ 20 Masterclass on udemy
ROS packages for Turtlebot3
Contains some Verilog code written or tested by me.
This repo consists of some VHDL code that I wrote or found useful.
A repo containing some of my code from Xilinx Vivado HLS tool.
Examples inspired from "vsomeip in 10 minutes" https://github.com/COVESA/vsomeip/wiki/vsomeip-in-10-minutes