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FPGA-model for generate echo-signals from fluctuating targets

Shell 0.31% JavaScript 0.12% Tcl 0.11% VHDL 89.09% Verilog 10.27% MATLAB 0.02% Forth 0.01% Pascal 0.01% Stata 0.06% HTML 0.01% Batchfile 0.01%

swerling-model's Introduction

Swerling-model

FPGA-model for generate echo-signals from fluctuating targets in Vivado Design Suite 2016.4

Files:

  • mat/rom_coe_gen.m - MATLAB file for generate ROM coefficients
  • mat/read_noise.m - MATLAB file for reading and analysis of generated echo-signals
  • swerling_model_rom.srcs/sources_1/ip/log_fun_65536x16/ - IP block of ROM 65536x16 (include linked files)
  • swerling_model_rom.srcs/sources_1/ip/square_root/- IP block of square root function (include linked files)
  • swerling_model_rom.xpr - project
  • swerling_model_rom.srcs/sources_1/new/swerling_model_rom.vhd - vhdl source file
  • swerling_model_rom.srcs/sources_1/new/swerling_model_rom_tb.vhd - vhdl testbench file

Paper: https://yadi.sk/d/_myRHwXUYjA4ag

swerling-model's People

Contributors

tnm-git avatar

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