rutgers-risc-v / risc-v-processor

Rutgers 2019 ECE Capstone - RISC-V Processor: RV32I, 5-stage pipelined

RISC-V-Processor

Video
Poster
Rutgers Capstone Website

Our group has implemented a RISC-V processor on a field-programmable gate array (FPGA). The implementation is a system comprised of a RISC-V processor with an interactive terminal interface. The processor is a single-core, pipelined, 32-bit RV32I processor, which includes the base instruction set I. The processor contains a full single issue, in-order five stage pipeline with hazard detection. Pipelining splits the processor into 5 stages, each with a different purpose: fetching an instruction, decoding the instruction, executing the instruction, accessing memory, and storing instruction output to a register. The pipeline allows the processor to compute five instructions in different stages of execution on the same clock cycle. This processor is written in VHDL and is RISC-V compliant. We have included a suite of additional features and software to showcase some of the possible applications of our processor. To interact with the processor, we have implemented a terminal interface on a VGA display that enables users to run programs as a demonstration of some of its capabilities. These programs accept user input from interfaces on the FPGA board and display output to the user, show graphics using ASCII text, and even run small games utilizing the terminal. This project has been featured as an entry into the Harris Corporation 2019 Senior Project Mentor Program, and we have received guidance from industry experts on how to design and implement our project.