sej7278 / kicad-panelizer Goto Github PK

OS: Win 10
KiCad version: 5.1.4
Python 3 installed.

When I try to run the script with ./panelizer.py --panelx=100 --panely=100 /path/to/source_board.kicad_pcb, i the the error from the title:

Traceback (most recent call last):
  File "...\panelizer.py", line 6, in <module>
    import pcbnew
ModuleNotFoundError: No module named 'pcbnew'

Any insight into what I'm missing?

EDIT: I added the full command output.

Most fabs want vscore lines on the Edge.Cuts layer, this means that the panel has various lines for rails and vscores that aren't strictly board outlines and this causes an error with the 3Dviewer as it cannot identify the board outline, it also fails the DRC.

Potentially we could move from lines to a series of (overlapping?) rectangles that would then be polygons. Not sure if that would help though.

Also could do with a way of detecting the line width of the Edge.Cuts layer, at the moment we're defaulting to 1.0mm same as KiCad.

Tooling holes - fiducials and 3mm holes on rails (mostly written by @willemcvu)

reference: https://www.worthingtonassembly.com/panelization

It would be nice to be able to add a small gap between the boards in the panel, as an option.
Useful if prototype PCB made ad-hoc, and then panel is cut by diamond circular saw.

More advanced version of HORIZONTAL_EDGE_RAIL_TEXT to include board title, company title, company logo etc. Panel ID stuff.

Potentially we could read this from a page layout description file or the pcb title block itself

ref: http://docs.kicad-pcb.org/doxygen-python/classpcbnew_1_1TITLE__BLOCK.html

print("revision:", board.GetTitleBlock().GetRevision())
print("company:", board.GetTitleBlock().GetCompany())
print("title:", board.GetTitleBlock().GetTitle())
print("date:", board.GetTitleBlock().GetDate())

Update: mostly done:

Will be adding pics in a few hours.

When panelizing a design that has routed and V-scored edges, the script ignores any edges that don't make up the rectangular bounding box of the board.

Is there a way to pull back copper layers to the pullback distances so if the user presses "b" on the panel, it doesn't get wrecked (by copper getting too close to V-scores)

Maybe make a "DRC" that checks if copper is too close to V-score lines.

This may be related to why when using a non Edge.Cuts V_SCORE_LAYER the panel merges into one giant board when you do a zone refill.

I am using KiCad 6.0.2 to generate a panelized version of a simple PCB. The tool generated a 5x4 matrix of boards within the 100x100mm constraints, but when opened with KiCad's standalone PCB editor only the top left PCB was routed, all the others had rats nests. Am I missing something obvious?

The report could go into the generated panel file as a text field or somesuch, preferably a layer that doesn't automatically get added to 3d viewer or gerbers, also outside of the panel.

Would allow for more flexible text sizes

The script does not seem to cope with Kicad 8.x PCBs.

What should be changed to make it work with the newest KiCad ?