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loadelf is not working about riscv_vhdl HOT 4 CLOSED

sergeykhbr avatar sergeykhbr commented on June 1, 2024
loadelf is not working

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Comments (4)

sergeykhbr avatar sergeykhbr commented on June 1, 2024

I will check how the latest modifications affected on FPGA target. Did you use the latest version?

Could you also make the following steps to get additional information:

  • Halt FPGA before loading new image (because of when loading is finished loadelf command restores CPU previous state).
  • Check that npc register is equal to RESET_VECTORE (value 0x40)
  • Read or dump part of memory starting from 0x10000000 (in hex format) and compare it with the generated helloworld.hex file.

Thank you

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sergeykhbr avatar sergeykhbr commented on June 1, 2024

I've just tried to build and debug FPGA (ML605) target using Ethernet/UDP TAP and it works fine. The only changes that I've made were the following things:

  • Add recently created dcom_uart.vhd file into misclib of the ISE project.
  • I also wrote 1 into pnp->fwid register by sending command 'write 0xfffff004 4 0x1' before loading elf-file. It allows to avoid default image (zephyr) re-loading after soft-reset (see boot/main.c).

Could you provide more information about your setup?

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southlife avatar southlife commented on June 1, 2024

Thanks for your fast response.

I had test with latest pre-built image(riscv_vhdl-master\rtl\bit_files\v6.0\virtex6_ml605\riscv_soc_river_40mhz_zephyr16_v6.bit) and ML605 FPGA board.

  1. When I halt the target before loading elf file, NPC value is 0x10004258 not 0x40.
  2. Write 0x1 to 0xfffff004 for bypassing image_copy function in boot-up time as you mentioned.
  3. And run [loadelf helloworld] command
  4. Then UART0 display the TRAP code as following.

shell> Boot . . .OK
ADC clock not found. Enable DIP int_rf.
mcause:0000000000000002,mepc:0000000010000000

But when I use the latest rtl code(rebuild fpga image in ISE) that you have updated yesterday(added dcom_uart.vhd, dcom_jtag.vhd, tap_jtag.vhd),
It works fine as following!

Boot . . .OK
ADC clock not found. Enable DIP int_rf.
Hellow World - 1!!!!
mcause:0000000000000002,mepc:00000000000000de

I think it would be a good idea to add writing 0x1 at 0xfffff004 to the tutorials

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sergeykhbr avatar sergeykhbr commented on June 1, 2024

Thank you for your feedback.
I'll move initialization of register pnp->fwid into the boot code.

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