sergeykhbr / riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

System-On-Chip template based on synthesizable processor compliant with the RISC-V architecture.

Howto build FPGA bitstream or RTL simulation:

• To build KC705 bitstream file:

    $ cd sv/prj/impl/kc705
    $ make
  

• To build and run full system unisim RTL simulation:

    $ cd sv/prj/impl/asic_sim
    $ make build
    $ make gui
  

• To build and run precise SystemC simulation (see github actions):

    $ cmake -S ./debugger/cmake -B build
    $ cd build
    $ make
    $ cd linuxbuild/bin
    $ ./run_sysc_river_x1_gui.sh
  

Note: Information related to VHDL source code is obsolete and currently is updating.

This repository provides open source System-on-Chip implementation based on open source RISC-V specifications. SOC project includes general set of peripheries, FPGA CADs projects files, own implementation of the Windows/Linux debugger and several examples that help to run your firmware on almost any FPGA boards. Satellite Navigation (GPS/GLONASS/Galileo) modules were stubbed in this repository and can be requested separately.

What is River CPU?

That's a VHDL RISC-V ISA implementation used in a several projects including the multi-sytem Satellite Navigation receiver. It is great for an embedded applications with active usage of 64-bits computations (like DSP).
River CPU includes the following tools and features:

1. Source code
   • /debugger/cpu_fnc_plugin - Functional RISC-V CPU model.
   • /debugger/cpu_sysc_plugin - Precise SystemC RIVER CPU model.
   • /rtl/riverlib - synthesisable VHDL model of a 64-bit processor compliant with the RISC-V architecture.
2. Floating Point Unit (FPU)
3. Multi-Core configuration
4. Advanced debugging features
   • Test Access Points (TAPs) via Ethernet, UART and JTAG in one system.
   • Compatible with the Standard RISC-V debug specification.
   • System Bus tracer
   • Pipeline statistic (CPI, HW stacktrace) in a real-time on HW level.
   • Plug'n'Play information

You can find several demonstration videos here of working with the Dual-Core SoC on FPGA and with the emulated platforms.

System-on-Chip structure

SoC documentation in .pdf formats.

Performance

Performance analysis is based on very compact Dhrystone v2.1. benchmark application available as the bare-metal test in $(TOP)/example/dhrystone21 folder and entirely ported into Zephyr shell (see animated gif below). Benchmark was executed with enabled (-O0) and disabled (-O2) optimization to define HW and GCC-compiler advantages. All sources are available and could be run on the simulator or on the different FPGA targets.

Target	Git tag	Dhrystone per sec, -O0, 60 MHz	Dhrystone per sec, -O2, 60 MHz	Information.
RISC-V simulator	latest	76824.0	176469.0	GCC 7.1.1 with the compressed instructions set.
RISC-V simulator	latest	77719.0	184074.0	GCC 8.3.1 with the compressed instructions set.
"River" CPU	latest	48581	135432.0	GCC 8.3.1 with the compressed instructions set.
ARM simulator	latest	78451.0	162600.0	arm-none-eabi-gcc 7.2.0, ARM ISA only.
Cortex-R5 ARM	No	20561.0	42401.0	arm-none-eabi-gcc 7.2.0, custom FPGA system: Single-Core, MPU enabled, Caches disabled.
Cortex-R5 ARM	No	54052.0	132446.0	arm-none-eabi-gcc 7.2.0, custom FPGA system: Single-Core, MPU enabled, Caches enabled.
Cortex-M3 Thumb2	arm_vhdl	soon	soon	arm-none-eabi-gcc 7.2.0, custom FPGA system
"LEON3" SPARC V8	No	48229.0	119515.0	sparc-elf-gcc 4.4.2, custom FPGA system.

Access to all memory banks and peripheries for all targets (including ARM and Leon3) is made in the same clock domain and always is one clock (without wait-states). So, this benchmark result (Dhrystone per seconds) shows performance of the CPU with integer instructions and degradation of the CPI relative ideal (simulation) case.

CPU	Clocks-Per-Instruction, CPI	Description.
Cortext-R5	1.22	This is dual-issue processor capable to execute a pair of instructions per one clock. It's a very good but quite expensive CPU.
LEON3	1.5	CPI information from here.
River	1.35	Free-to-use and highly customizable CPU. I/D caches are enabled: 4-ways, 16 KB each. Reference Manual.
Cortex-M3	soon	RTL is under development.

Since the tag 'v7.0' RIVER CPU is the main processor in the system and all issues related to Rocket-chip instance will be supported only by request.

Repository structure

This repository consists of three sub-projects each in own subfolder:

• rtl is the folder with VHDL/Verilog sources of the SOC including synthesizable processors "Rocket" and "River" and peripheries. Source code is portable on almost any FPGA is due to the fact that technology dependant modules (like PLL, IO-buffers etc) instantiated inside of "virtual" components in a similar to Gailser's GRLIB way.
  Full SOC design without FPU occupies less than 5 % of FPGA resources (Virtex6). "Rocket-chip" CPU itself is the modern 64-bits processor with L1-cache, branch-predictor, MMU and virtualization support.
  This sub-project also contains:
  • fw_images: directory with the ROM images in HEX-format.
  • prj: project files for different CADs (Xilinx ISE, ModelSim).
  • tb: VHDL testbech of the full system and utilities.
  • bit_files: Pre-built FPGA images for ML605 and KC705 boards.
• examples folder contains several C-examples that could help start working with the RISC-V system:
  • boot is the code of the Boot Loader. It is also used for the SRAM initialization with the FW image and it allows to run examples on FPGA without using the debugger and external flash memory.
  • helloworld the simplest example with UART output.
  • isrdemo example with 1 second interrupt from timer and debug output.
  • zephyr is ported on RISC-V 64-bits operation system. Information about this Real-Time Operation System for Internet of Things Devices provided by Zephyr Project. Early support for the Zephyr Project includes Intel Corporation, NXP Semiconductors N.V., Synopsys, Inc. and UbiquiOS Technology Limited.
• debugger. The last piece of the ready-to-use open HW/SW system is Software Debugger (C++) with the full system simulator available as a plug-in. Debugger interacts with the target (FPGA or Software Simulator) via Ethernet using EDCL protocol over UDP. To provide this functionality SOC includes 10/100 Ethernet MAC with EDCL and Debug Support Unit (DSU) devices on AMBA AXI4 bus.

Step I: Simple FPGA test.

You can use the pre-built FPGA image (for Xilinx ML605 or KC705 board) and any serial console application (putty, screen or other) to run Dhrystone v2.1 benchmark as on the animated picture below.

1. Unpack and load file image riscv_soc.bit from /rtl/bit_files/ into FPGA board.

2. Connect to serial port. I used standard console utility screen on Ubuntu.

    $ sudo apt-get install screen
    $ sudo screen /dev/ttyUSB0 115200
   

3. Use button "Center" to reset FPGA system and reprint initial messages (or just press Enter):

To end the session, use Ctrl-A, Shift-K

Step II: Build and run Software models with GUI.

How to build simulator from scratch see here

It should look like the following:

There's dependency of two others open source projects:

• Qt-libraries
• SystemC library

Step III: Build FPGA image

Default VHDL configuration enables River CPU with full debug support.

1. Open ML605 project file for Xilinx ISE14.7 prj/ml605/riscv_soc.xise or KC705 project file for Xilinx Vivado prj/kc705/riscv_soc.xpr.
2. Edit configuration constants in file work/config_common.vhd if needed. (Skip this step by default).
3. Use rtl/work/tb/riscv_soc_tb.vhd" testbench file to verify full system including CPU, UART, Timers, Ethernet, GPIO etc.
4. Generate bit-file and load it into FPGA.

Doxygen project documentation

http://sergeykhbr.github.io/riscv_vhdl/

riscv_vhdl's Issues

Error compiling debugger

First of all, thanks for all your work and for sharing it!

I have the following error relate to _cpu_sysc_plugin when I try compiling the debugger:

#####################################################################
#####################################################################
../src/cpu_sysc_plugin/rtl_wrapper.cpp: In member function ‘void debugger::RtlWrapper::comb()’:
../src/cpu_sysc_plugin/rtl_wrapper.cpp:154:27: error: switch condition has type bool [-Werror=switch-bool]
switch (r.state.read()) {
^
cc1plus: all warnings being treated as errors
make_cpu_sysc_plugin:110: recipe for target '../linuxbuild/obj/plugins/cpu_sysc/rtl_wrapper.o' failed
make[1]: *** [../linuxbuild/obj/plugins/cpu_sysc/rtl_wrapper.o] Error 1
mkdir: created directory './../linuxbuild/obj/plugins/gui'
####################################################################
####################################################################

I can skip this error removing '-Werror' in the Makefile 'make_cpu_sysc_plugin' but when I run './_run_functional_sim.sh', I can't see in console 'Hello world' when I load the program helloworld(compiled using with your elf2raw) as show here:

I'd like to add that I can load helloworld.hex in the ML605, changing CFG_SIM_FWIMAGE_HEX in config_v6.vhd and everything works perfectly, I can see 'Hello world' in the serial console on my pc. The problem is with the simulator/debugger.

Regards,
Frank.

Generating bit file for boot up using debugger

I am using a linux machine for fpga implementation of river core with freertos.
As you suggested, i changed COM3 to ttyUSB0 in debugger/targets/fpga_gui.json
After this, when i tried to generate bit file, i got the error that it can not access bin folder in riscv_vhdl/examples/dhrystone/makefiles/
So, i checked the repository and saw that the folder name was changed from bin to binarm
I renamed the folder to bin
As per your suggestions, I also did the following:
1. desabled FPU
2. commented CFLAGS += -march=rv64imac -mabi=lp64 statement in examples/bootrom_tests/makefiles/make_bootrom_tests

After this, when I tried to generate the bit file, it gave the error that I am trying to access the dhrystone21.hex after the limit of the file.
After further debugging, I found that the ROM_LENGTH calculation in rom_inferred.vhd file exceeds the dhrystone.hex file limit.
Can you please check these issues and let me know what am I doing wrong?

Uart Conf

we want to use debugger for booting zephyr, In .ucf file you have connected uart1 to usb-uart convertor where as debug uart goes to LPC, So do we need to swap these as debugger is not able to connect uart in present situation.

The software models with GUI closes automatically

If I run ./_run_functional_sim.sh or ./_run_systemc_sim.sh, it works fine for 2-3 mins. But, after 2-3 mins, the window closes automatically. The terminal messages are:

[example0]: Plugin post-init example: attr1_='This is test attr value'
[CoreService]:

---

RISC-V debugger
Author: Sergey Khabarov - [email protected]
Copyright 2016 GNSS Sensor Ltd. All right reserved.

---

[example0]: This is exampleAction(): val=0000cafe
<led[7:0]> 01h
<led[7:0]> 02h
<led[7:0]> 03h
<led[7:0]> 04h
Boot . . .OK
***** BOOTING ZEPHYR OS *****
riscv# *** Error in `./appdbg64g.exe': double free or corruption (out): 0x00007f4d8805f1d0 ***
./_run_functional_sim.sh: line 3: 7880 Aborted (core dumped) ./appdbg64g.exe -c ../../targets/functional_sim_gui.json "$@"

when the window closes, the terminal also stops working. If I try to run it from a different terminal, it appears for 3-4 secs and then closes. But, If I wait for 15-20 mins and then run it, it again works for 2-3 mins. Why is this happening? I am working on ubuntu 14.04.

Problems with building (or rather starting) the debugger

Dear Sergey,

first of all thank you for creating this amazing project. I can't wait to put my hands on it and use it. Right now there seem to be some bugs when building (or rather starting) the debugger.

I installed qt5.7 and systemC from source as described in the README. I don't get any bugs during the building process of the debugger. But when I am trying to start it using some of the bash scripts I always get the same error:

eve@ubuntu: riscv_vhdl/debugger/linuxbuild/bin$ ./_run_functional_sim.sh 

Class GuiPluginClass not found

Error: can't instantiate configuration

Also there is a minor bug when creating the bash scripts. It seems that instead of adding the line break itself it just adds the '\n' to the script, which results in just one line, which cannot of course not be executed.

#!/bin/bash\nexport LD_LIBRARY_PATH=$(pwd):$(pwd)/qtlib\n./appdbg64g.exe -c ../../targets/functional_sim_gui.json "$@"

I am using Ubuntu 18.04

Thanks for any help :)

problem compilation with options: -march=rv64imafd -DFPU_ENABLED

Здравствуйте! Попробовали пересобрать helloworld с функцией сложения двух чисел типа double. Использовали компилятор riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14 от SiFive с опциями -march=rv64imafd -DFPU_ENABLED.
В helloworld.dump в разделе функции fadd присутсвует недокументированная команда fmv.d. При моделировании в данном месте возникает исключение из-за нелегальной операции.

Как можно решить данную проблему?

Листинг модифицированной части helloworld.c прилагаю:

double fadd(double a, double b){
double c=a+b;
return c;
}

void helloWorld() {
char ss[256];
int ss_len;
ss_len = sprintf(ss, "Hellow World - %d!!!!\n", 1);
print_uart(ss, ss_len);
fadd(10,10);
}

Zynq-7000

Zynq-7000 implementation is ready to use?
And what it is the RISC-V specification version and extensions?

Thank you!

How to generate VCD files of bare-metal dhrystone with _run_systemc_sim.sh?

Hi Sergey,

Thanks for sharing this nice project.

I assume RISC-V SystemC model is CABA(Cycle-Accurate Bit-Accurate), right?

And I want to view it's waveform of some workloads, e.g. the pre-built dhrystone21.elf.
So, I managed to build the master branch code successfully (some modifications to satisfy compilation and added some missing files in the makefile), then I tried to add loading dhrystone21.elf with below modification:

But, after waiting some seconds, seems nothing have been run, please check the attachment for log.
sc.log

And below is screenshot of the pop-up Universal platform simualtor:

Any suggestions to correctly dump VCD waveform?

Thanks,
Cai Yu

Bare-metal Rocket Chip

Hello,

I was wondering if it is possible to run bare-metal applications with rocketchip? I wanted to simply flash a program written in C without using bootloader and flashing linux image to ROM. If it is not possible please point me to some details (docs, readings etc.) about it.

elf2raw64 и .shstrab

Сергей, здравствуйте! Собрали elf2raw64 из исходников. При конвертации выдается ошибка:
err: undifined .shstrab section.

Возможно мы не правильно elf собираем?
В качестве тулчейна используем SciFive пресобранный со студией.

Хотим запустить helloworld.

Building bootimage fails on linux using riscv-gcc 5.3.0

When running make to build the bootimage I get the following error:

riscv64-unknown-elf-gcc -c -g -static -std=gnu99 -O0 -fno-common -fno-builtin-printf -march=RV64IMA -msoft-float -I../../common -I../src ../src/main.c -o ../linuxbuild/obj/main.o
riscv64-unknown-elf-gcc -c -g -static -std=gnu99 -O0 -fno-common -fno-builtin-printf -march=RV64IMA -msoft-float -I../../common -I../src ../src/trap.c -o ../linuxbuild/obj/trap.o
riscv64-unknown-elf-gcc -c -g -static -std=gnu99 -O0 -fno-common -fno-builtin-printf -march=RV64IMA -msoft-float -D__ASSEMBLY__=1 -I../../common -I../src ../src/crt.S -o ../linuxbuild/obj/crt.o
riscv64-unknown-elf-gcc -T test.ld -nostdlib -nostartfiles ../linuxbuild/obj/main.o ../linuxbuild/obj/trap.o ../linuxbuild/obj/crt.o -o ../linuxbuild/bin/bootimage -lgcc -lc -lm
/mnt/ultrabay/paco-env/riscv-tools/lib/gcc/riscv64-unknown-elf/5.3.0/../../../../riscv64-unknown-elf/bin/ld: /mnt/ultrabay/paco-env/riscv-tools/lib/gcc/riscv64-unknown-elf/5.3.0/../../../../riscv64-unknown-elf/lib/libc.a(lib_a-memcpy.o): can't link hard-float modules with soft-float modules
/mnt/ultrabay/paco-env/riscv-tools/lib/gcc/riscv64-unknown-elf/5.3.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /mnt/ultrabay/paco-env/riscv-tools/lib/gcc/riscv64-unknown-elf/5.3.0/../../../../riscv64-unknown-elf/lib/libc.a(lib_a-memcpy.o)

Changing the CFLAGS back to -O2 seems to fix the problem.

Cheers,
Bastian

Do you plan to write FPU for River CPU?

Your work is very amazing. Since I find it really hard to understand Chisel codes for Rocket-chip, your work helps me a lot on studying the CPU design. Have you considered designing a single/double-precision FPU? The FPU used by Rocket-chip is also written in Chisel and the developers don't write any documents about it. So it's also difficult to understand.

riscv_soc_tb Simulaton

Hi,
Thanks for your efforts.

I wanted to run a simulation as mentioned in http://sergeykhbr.github.io/riscv_vhdl/verification_page.html#sim_tb_link and unable to find the mentioned testbench file or a document that explains the expected behavior.

On the other hand, I tried to run through the following path iscv_vhdl/vhdl/rtl/prj/sim, after creating a questasim makefile the mimics the committed xilinx makefile. But, I do not understand what is the expected behavior while moving from a JTAG test to another, is that documented anywhere?
Also I noticed that both Ethernet & UART enables are instantiated with 0, is that intended?

That's the waveform output

showing CPU is turned off

I followed the steps present in Readme for setting debugger
and ran _run_functional_sim.sh
after this a prompt cmd# came in that i tried loaded helloworld
cmd# loadelf /home/riscv/helloworld
after this it showed reading some section
after this i pressed F5 but its showing
[25867098, "core0", "../src/common/generic/cpu_generic.cpp:428 CPU is turned-off"]

what am i doing wrong
I reconfigured ip address to 192.168.0.53
using command
sudo ifconfig eth0 192.168.0.53 netmask 255.255.255.0

Cannot find _run_functional_sim.sh

Cannot find _run_functional_sim.sh in debugger folder
I Am following your readme and trying to do
"Build and run custom FW like 'Hello World' example."
but am not able to find debugger/linuxbuild/bin/_run_functional_sim.sh

Communicating with the ML605 Board (v8.0)

Hello,

I'm having an issue or misunderstanding for communicating with the processor via UART. I downloaded the bitstream v8.0 into the ML605 board using iSE Impact, opened the UART channel on my computer and when I press RESET, I receive only a byte 00 on UART.

Also, it is possible to generate the bitstream for the ml605 board in the v11?

Thanks

Run Hello world example on VC707 board

Hello,
Thanks for this great work, I appreciate the whole work. It is extremely beneficial.
Actually,I removed the constraint file of KC705 board, and I used the constraint file of VC707 board, and I did the matching between them. Fortunately, the bit stream is written successfully and uploaded on the board.
However, I need to test the processor on the board, so I chose the simple hello world example using the UART module, but I don't know what should I do to test hello world on the board. I know that I need a compiler to produce HEX file format for the C program and then put the path for the generated HEX file somewhere in the code (I think in the sram module), so Kindly can you tell me the steps to test the hello world example because I am not able to get this point from the repository.
Thank you in advance,
Mina

Potential ICache Bug

It seems that the cache can request two read addresses in sequence, without waiting for the first one to come back. I see this occur often on returns and jumps; causing the processor to enter an undefined state.

In other words, ARVALID is held high for two clocks, and the address is different on each clock, causing 2 requests. As near as I can determine it is caused by r.double_req in icache.vhd.

I would be happy to provide more information if nesassary.

A few questions

Thanks again for all your help. I just have a few questions concerning the River core:

• It seems that there is just 1 or 2 lines available in the caches. Is there actually a configurable cache size, or is it currently fixed?
• Can RISCV_ARCH be changed to 32 to support the 32bit RISC-V ISA? I see some things that appear to suggest it is hardcoded to 64 bits.
• It seems that the debug unit slave could be connected to a JTAG to AXI master, and then programmed via OpenOCD allowing for gdb debugging. Is there a defined protocol used within the debug module?

What configuration did you use for Rocket core?

Version 7 and below included a pre-built Rocket core. Can you make available the configuration files for this version? I'm guessing you customized it a bit before generating from the Chisel code.

Thanks,
Teadotjay

slurm dependency

I'm trying to get the design to compile & simulate - it looks very complete! But... More advanced SW engineers use slurm, but a lot of people don't, especially HW engineers. I've never used it. Could you please add a RTL compile/simulate process that doesn't require slurm?

Openning ttyUSB0 at 115200 . . .failed"

I am trying to run application debugger on top of fpga.
so i executed fpga_gui.sh and used loadelf tool to load the zephyr.elf onto fpga but it says
[0, "port1", "../src/libdbg64g/services/comport/com_linux.cpp:152 fopen() failed"]
[0, "port1", "../src/libdbg64g/services/comport/comport.cpp:128 Openning ttyUSB0 at 115200 . . .failed"]
[0, "edcltap", "../src/libdbg64g/services/debug/edcl.cpp:99 No response. Break read transaction[1] at 80090000"]
[0, "udpedcl", "../src/libdbg64g/services/debug/udp_dbglink.cpp:224 sendto() failed

this never stops
and also LED @ ethernet do not blink at host system side
i have used sudo ifconfig eth0 192.168.0.53 netmask 255.255.255.0
to change the ip of my pc
I also changed COM3 to ttyUSB0 as you have mentioned since my host is ubuntu 18.04
is there any other source file that i need to change.
please tell what am i doing wrong?

Build debugger with GUI failed: libdbg64g.so undefined reference

Hi Sergey! great project to learn from you!! I am running into a problem building and running Software models with GUI (Step 2 in your project). libdbg64g.so gives undefined reference and caused error when I run "make" in the "~/riscv_vhdl/debugger/makefiles" directory. Below is a screenshot of the problem. Can you give any hint on solving this? Thanks.

simulation of kc705_tb

Hello Serge,
You have done great work in this project. I really appreciate it. However, I am now stuck in the simulation step of kc705 testbench. I followed these steps to simulate it. I have gone to kc705_sim directory and then run make build command and then make gui but it is not responding. It is displaying this message "make: srun: No such file or directory". Do you have any idea how to get it working?
Thanks in advance.

gptimer alignment in the second timer is not correct

Hello,

In riscv_vhdl/rtl/misclib/axi4_gptimers.vhd while reading and writing register data for timer (control, init_value and value) you are adding 16 + 8*k while k is the index of timer (0 or 1) to the address to align the registers.

this is the typedef map for the timers in map_gptimers.h file
typedef struct gptimer_type {
volatile uint32_t control;
volatile uint32_t rsv1;
volatile uint64_t cur_value;
volatile uint64_t init_value;
} gptimer_type;
typedef struct gptimers_map {
uint64_t highcnt;
uint32_t pending;
uint32_t rsvr[13];
gptimer_type timer[2];
} gptimers_map;

So you are adding 16 for (highcnt, pending and rsvr[13]).
the size of them is (8 + 4 + (4*13)) = 64
64 / 4 = 16 and this is what you done in axi4_gptimers.vhd

And you are adding 8 for (gptimer_type).
the size of gptimer_type is (8 * 3) = 24
24 / 4 = 6 and you are writing 8 in axi4_gptimers.vhd

I tryed to use the second timer and I noticed that it is not working. So, after debugging I found that it should be 6 instead of 8 in map_gptimers.h, So I changed it and it works fine.

If I mistake something please correct me.

Thanks

loadelf is not working

Hi, sergey.

Thank you for making River system.
I am following the tutorial now.
However, there are parts that do not work so I leave a question.

[loadelf helloworld] command is work well in Simulator(_run_functional_sim.sh).
But, in the FPGA(_run_fpga_gui.sh), the loadelf command is not work.

Here is the log when I run the command.

riscv# loadelf /test/helloworld
riscv# err: undefined .shstrtab section
[loader0]: Reading '.text' section
[loader0]: Reading '.rodata' section
[loader0]: Reading '.rodata.cst16' section
[loader0]: Reading '.rodata.str1.8' section
[loader0]: Reading '.data' section
[loader0]: Reading '.got' section
[loader0]: Reading '.got.plt' section
[loader0]: Reading '.sdata' section
[loader0]: Reading '.sbss' section
[loader0]: Reading '.bss' section
[loader0]: Loaded: 33808 B
[edcltap]: ../src/libdbg64g/services/debug/edcl.cpp:154 No response. Break write transaction.
[edcltap]: ../src/libdbg64g/services/debug/edcl.cpp:154 No response. Break write transaction.
[edcltap]: ../src/libdbg64g/services/debug/edcl.cpp:154 No response. Break write transaction.
[edcltap]: ../src/libdbg64g/services/debug/edcl.cpp:154 No response. Break write transaction.
[edcltap]: ../src/libdbg64g/services/debug/edcl.cpp:154 No response. Break write transaction.

As you can see, when I run loadelf, edcl does not work properly.
Does it work right in the FPGA?

Rtos port on RISC-V

Hello,

I'm doing an rtos port on RISC-V and currently working on the fpga-zynq/rocket-chip directory of Berkeley's.

Could you please provide instruction to how you used Vivado tools to generate another boot.bin which contains another os than linux with the rocket chip ? Did you use this directory at all ?
What kind of files are necessary to have both the rocket cores and another os into the same boot.bin ?

Thank you very much

Regards

riscv_soc_tb crashes in Vivado Simulator

When I execute the simulation from Vivado 2017.4, in the KC705 project, it produces the following errors:

Command failed: Simulator command interrupted.

Simulator engine not responding.
The simulator has terminated in an unexpected manner. Please review the simulation log (xsim.log) for details.

I'm not sure what may be the cause? Does this occur on your end?

Adding a Master peripheral

I want to add a new slave peripheral to Riscv, and I took SRAM as reference to know the modules and packages that I should modify, and I found that I should add:-

1. Index, start and end address in the memory address mapping in types_bus0_pkg.
2. Add a new device id in types_amba_pkg for my new peripheral.
3. Define the size of the peripheral in config_target_pkg.
4. Define the new slave peripheral in riscv_soc_pkg which I can't understand what this number given to the peripherals represent and to which module this number is used "I think this is the missing part that this number should be mapped to another module and get some information from this module, so if you can clarify what is the idea behind this number "SOC_PNP_SRAM"".
   Do I need to adjust any other modules or packages?

How to build River CPU?

Hello,

I understand that this is a template for instantiating the CPU on an SoC, however I am wondering if it is possible to just instantiate the River CPU as a standalone entity?

I see this issue: #9

However I am wondering if it is possible to remove any extra components? Thanks for any help!

Boot procedure bypass ROM FW copy to SRAM

Hi Sergey,

Thanks again for making this RISCV design open to design community.

I'm trying to add a new peripheral and add programming.

So I modified the ADDRESS MAP and logic to add this peripheral.

Is there a shortcut way to add my new code right after

"Registers initialization"

and before

"Copying ROM FW Image into internal SRAM"
"Go to SRAM entry point 0x10000000 in user mode"
"Initialization of the "Interrupt Registers" by proper handler"
"Initialization of the UART"
"Start main task"
?

The sample code also has GPIO writing to the LED.
How to make new code also work before or after GPIO writing to LED.

For simulation, the ROM FW Image copying into internal SRAM is consuming lots of
simulation time and doesn't make for quick and easy debug of my code and logic.

Any other recommendations ?

Thanks,

David

freertos port for river core

Hi, I want to port freertos on the river core,so is there any links where i can refer or if you have done it would you share the steps? . I have gone through the freertos site

GNSS module

Hi there,

As you mentioned in the README and I found from the "gnsslib" folder, it seems there are RTL files and firmware for GNSS SDR receivers. I am quiet interested on it, as I am considering to build GNSS receivers with potential applications in small satellites. Are you convenient to share the RTL files and firmware? Thanks.

compiling errors

Hi ,all

I want to compiling boot (riscv_vhdl\rocket_soc\fw\boot),but find some errors maybe causing gun-toolchain version , please experts explanation ! Thanks~

Generate failed of helloworld hex file

Hi all,

I have used "make" command in the directory of "riscv_vhdl\rocket_soc\fw\helloworld\makefiles" want to generate helloworld hex file but the output is all zero. Besides，the warning cannot solve it ! please tell me the reason.

how to generate bitstream file by myself ?

Hi Sergey,

At first，thanks for your source code about risc-v cores.

I know I can directly use your project at ISE or Vivado(riscv_vhdl/rocket_soc/prj/) but I want to synthesis in vivado by myself at xilinx VCU118 Board. Can you tell me which vhdl files need to add my project and other attention items?

Thanks you very much !

can you run linux?

Nice project! can you run linux on it?

missing packages?

I'm having issues compiling the vhdl code, and it seems to me that it's because there are packages missing. For example, the file riscv_soc_gnss.vhd tries to use rocketlib.grethpkg.all, but there is no grethpkg.vhd file in rocketlib. Am I missing something here?

Will this fit on an Avnet S6microboard (Spartan6 LX9)

MMU Support?

Hello, I was wondering if the River core (or perhaps integration of Rocket) supports any form of mmu? Thank you

Any plans or suggestions for laticce or gowin fpga chips support?

Because it will be good and fun to have open source SoC on chips that supported by opensource tools!