shalan / ms_dmac_ahbl

A Direct Memory Access Controller (DMAC) with AHB-lite bus interface

MS_DMAC_AHBL

Direct Memory Access Controller (DMAC) with AHB-lite bus interface.

Interfaces

Ports

Port name	Direction	Type	Description
HCLK	input		System Clock
HRESETn	input		System Reset
IRQ	output	wire	IRQ line to the CPU
PIRQ	intput	wire	IRQ lines from peripherals requesting data transfer
HSEL	input	wire	Slave Port HSEL
HADDR	input	wire [31:0]	Slave Port HADDR
HTRANS	input	wire [1:0]	Slave Port HTRANS
HWRITE	input	wire	Slave Port HWRITE
HREADY	input	wire	Slave Port HREADY
HWDATA	input	wire [31:0]	Slave Port HWDATA
HSIZE	input	wire [2:0]	Slave Port HSIZE
HREADYOUT	output	wire	Slave Port HREADYOUT
HRDATA	output	wire [31:0]	Slave Port HRDATA
M_HADDR	output	wire [31:0]	Master Port HADDR
M_HTRANS	output	wire [1:0]	Master Port HTRANS
M_HSIZE	output	wire [2:0]	Master Port HSIZE
M_HWRITE	output	wire	Master Port HWRITE
M_HWDATA	output	wire [31:0]	Master Port HWDATA
M_HREADY	input	wire	Master Port HREADY
M_HRDATA	input	wire [31:0]	Master Port HRDATA

Slave Registers

Address	Description
0x00	Control Register 0: EN 8-11: Transfer trigger; One bit for each of the 4 sources; 0000 means software trigger 16-17: Source data type; 0: byte, 1: half word, 2: word 18: Source Address Auto increment 24-25: Destination data type; 0: byte, 1: half word, 2: word 26: Destination Address Auto increment
0x04	Status Register 0: Done
0x08	Source Address Register
0x0C	Destination Address Register
0x10	Data Size Register
0x14	SW Trigger Register
0x18	Frame Count Register

ms_dmac_ahbl's Issues

Add support for interrupts

Add support for receiving interrupts from peripherals. This way, the DMAC can transfer data from FIFO enabled peripherals every time the fifo is full w/o the need for interrupting the CPU. We are going to refer to the FIFO data as a frame.

FSM typo in last state

FSM leaves state WD_STATE whenever wait state injected because of the following condition. the state should stay at WD_STATE.

MS_DMAC_AHBL/hdl/rtl/MS_DMAC_AHBL.v

Line 136 in d638184

end else nstate = WA_STATE;

MS_DMAC_AHBL missing/wrong views for IP packaging

1. Missing hierarchy, bus wrapper should be under hdl/rtl/bus_wrapper
2. Missing verification

Wrong auto increment behavior

The latest RTL change to enable different incremental step is not behaving like expected.
For example with this configuration,

    SourceDataType (1); // half word
    DestinationDataType(1); // half word 
    sourceAddrAI(4); // word step
    destinationAI(2); // half word step

The below results should be expected if we are moving array_1 into array_2

moving the first half from the source into the array
However, it moves the first half from first word and second half from second word

Waveform snapshot.

Add feature to customize the increment value

The increment is set according to the data type. However it would be useful to customize increment value regardless of the data type

ahbl read write fsm missing default and runs 1 timer more than intended

The following FSM misses a default condition and it read and write 1 time after the done signal asserted.

MS_DMAC_AHBL/hdl/rtl/MS_DMAC_AHBL.v

Lines 121 to 137 in d638184

	always @*
	case(state)
	IDLE_STATE: if(TRIG_REG & CTRL_REG_EN)
	nstate = RA_STATE;
	else
	nstate = IDLE_STATE;
	RA_STATE: if(M_HREADY) nstate = RD_STATE; else nstate = RA_STATE;
	RD_STATE: if(M_HREADY) nstate = WA_STATE; else nstate = RD_STATE;
	WA_STATE: if(M_HREADY) nstate = WD_STATE; else nstate = WA_STATE;
	WD_STATE: if(M_HREADY) begin
	if(done)
	nstate = IDLE_STATE;
	else
	nstate = RA_STATE;
	end else nstate = WA_STATE;
	endcase