shariethernet / infiresv0.1-rv32ic-core

"Infires" is a series of RISC-V Cores developed using TL-Verilog. Infiresv0.1.x consists of different pipelined variants RV32I/C Cores.

Infiresv0.1-RV32IC-Core

About

"Infires" is a RV32X Series processor cores, written in TL-Verilog (Based on RV-MYTH Core). Due the unique features in Transaction Level Verilog, these cores can easily be modified to support other extensions or enhanced with branch predictors, hazard handlers etc., Due to the timing abstract nature of TL-Verilog, the pipelines can be quickly reconfigured or parametrised too. There are four cores developed namely

Variants

• Infiresv0.1.0 - RISC-V RV32I Non-pipelined Core

• Infiresv0.1.1 - RISC-V RVC (16-bit Compressed Instructions)

• Infiresv0.1.2 - RISC-V RV32I 4 stage pipelined Core

• Infiresv0.1.3 - RISC-V RV32I 6 stage pipelined Core

General Block Diagram of the core

1. Program Counter
2. Instruction Memory
3. Decode Logic
4. Register File
5. Arithmetic and Logic Unit
6. Write to Register File
7. Data Memory

Pipeline Stages

Infiresv0.1.2 - RISC-V RV32I 4 stage pipelined Core

1. Fetch
2. Decode
3. Register File Read
4. Execute in ALU, Register File Write, Branch

Infiresv0.1.2 - RISC-V RV32I 6 stage pipelined Core and Infiresv0.1.1 - RISC-V RVC

1. Fetch
2. Decode
3. Register File Read
4. Execute in ALU, Register File Write, Branch, Load , Jump
5. Data Memory
6. Write to data memory

All the cores are written in TL-Verilog. These are relatively simple cores which can be used for learning a chip design flow from front-end to tape-out as well as applications that demand low-power and dosent require high performance.

References

• RVMYTH Core