[Synth 8-439] module 'mmcm' not found about freedom

[richardxia]

You need to generate the Xilinx Mixed-Mode Clock Manager (MMCM) IP yourself if you're not using our Makefile scripts to synthesize the FPGA image. Here is a guide on how to do that in the Vivado GUI: http://users.wpi.edu/~rjduck/MMCM%20Vivado%20example%20Verilog.pdf

You can find the parameters that we used in https://github.com/sifive/fpga-shells/blob/2389e6e95717caca782e7444422da16fef687188/xilinx/arty/tcl/ip.tcl#L3-L13

[gobs-code]

@richardxia Thanks Richard,
The xilinx ip "mmcm"and "reset_sys" can find IP Catalog but "PowerOnResetFPGAOnly " I don't know can find where or need to write myself ? Please give me some hints~
Thank you again!

[mwachs5]

https://github.com/sifive/fpga-shells/tree/master/xilinx/common/vsrc

[gobs-code]

@mwachs5 Hi mwach,
I know some module under directory of freechipsproject/rocket-chip/vsrc and sifive/sifive-block but where is BootRom module , I cant find it !

[richardxia]

BootROM uses Chisel's sequential memory feature, so it does not refer to an existing Verilog module. You will need to use the vlsi_rom_gen script from rocket-chip to generate the Verilog file from the ROM parameters. See our Makefile rule for handling this:

freedom/bootrom/xip/Makefile

Line 38 in 22ee433

$(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@

[terpstra]

Looks like this is resolved.