Hi all,

I have some troubles understanding how the the DRAM is connected with the rest of the system inside U500 VC707 FPGA Dev Kit. Here below there is what I understood (with some guesses).

On VC707 board, DRAM are connected on an AXI bus. MIG is the memory controller, so the one in charge of interacting with DRAM. But how MIG is connected to the rest of the SoC? Through TileLink.

Looking inside Chisel code, and the verilog output, I was able to reconstruct this:

1. let's start from file:
   freedom/sifive-blocks/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
   class XilinxVC707MIG: here we find this connections: axi4 -> toaxi4.node -> xing.node -> node

2. file:
   /freedom/sifive-blocks/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
   the component XilinxVC707MIG described before is connected thorough
   val mem = Seq(xilinxvc707mig.node)

3. this val mem, (I GUESS) is defined (and connected to coreplex) inside file:
   freedom/rocket-chip/src/main/scala/rocketchip/RocketPlexMaster.scala

I don't want to annoy you too much guys, so please only tell me if what I wrote is correct, and if not, try to give me an idea of how things are organized.

Sorry for this question, and thank you for the answer!

Hi. I have to take a wire from dut.qspi(0).sck in ArtyShell.scala. I am trying to run e300 on Kintex. Since Kintex QSPI clock is only available through Startup2e. So I need to take wire from flash qspi clock and pass it to startup2e. In my opinion the good point to do that is ArtyShell line 176. I have tried but nothing is working. Can anybody tell how can I do it?

Hi all,

Is it possible to boot Linux from SD card on your system (i.e. VC707 FPGA Dev Kit)?
I'm searching something like the Rocket-chip untethered implementation made by LowRISC...

Thank you!

i generate the mcs file and download into fpga but the usb port doesnt print anything
i am sure that the usb port is ok because i once print message use the same fpga but with other soc mcs file
what i did:
cd /freedom
export RISCV=/riscv64-unknown-elf-gcc-20171231-x84_64-linux-centos6
make -f Makefile.e300artydevkit mcs

by the way, i do these command in the vivado tcl window because when i do it in terminal it ends up with launch the vivado then just halt there ,does it matter?

sed -r 's/(([A-Za-z0-9_]+),([A-Za-z0-9_]+))/`define \1 \2/' /Users/maXXXX/Desktop/sifive/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.prm >> /Users/maXXXX/Desktop/sifive/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.vh
sed: illegal option -- r
usage: sed script [-Ealn] [-i extension] [file ...]
sed [-Ealn] [-i extension] [-e script] ... [-f script_file] ... [file ...]
make: *** [/Users/maXXXX/Desktop/sifive/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.vh] Error 1

Dear all,

I notice the .xdc master file for Arty has a modification for QSPI clock, I think original file don't have the definition, that is

set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33  IOB TRUE } [get_ports { qspi_sck }];
create_clock -add -name qspi_sck_pin -period 20.00 -waveform {0 10}    [get_ports { qspi_sck }];

because you are actually suppose to work with STARTUPE2 instantiation, can you explain what is done here.

I am trying to port to different Arty board and not sure how to proceed here.

Will appreciate your comments,

Hi all,

We just cloned the freedom git repository (worked without errors) and want to compile the verilog sources as described in the readme file using "make -f Makefile.e300artydevkit verilog".
Make is starting but finishes with the error that the sbt-launch.jar ist not accessible.
See the log below.

Kubisch@TMC03 /cygdrive/d/projekte/risc-v/freedom
$ make -f Makefile.e300artydevkit verilog
make -C /cygdrive/d/projekte/risc-v/freedom/rocket-chip/firrtl SBT="java -jar /cygdrive/d/projekte/risc-v/freedom/rocket-chip/sbt-launch.jar" root_dir=/cygdrive/d/projekte/risc-v/freedom/rocket-chip/firrtl build-scala
make[1]: Verzeichnis „/cygdrive/d/projekte/risc-v/freedom/rocket-chip/firrtl“ wird betreten
java -jar /cygdrive/d/projekte/risc-v/freedom/rocket-chip/sbt-launch.jar "assembly"
Error: Unable to access jarfile /cygdrive/d/projekte/risc-v/freedom/rocket-chip/sbt-launch.jar
make[1]: *** [Makefile:23: /cygdrive/d/projekte/risc-v/freedom/rocket-chip/firrtl/utils/bin/firrtl.jar] Error 1
make[1]: Verzeichnis „/cygdrive/d/projekte/risc-v/freedom/rocket-chip/firrtl“ wird verlassen
make: *** [common.mk:26: /cygdrive/d/projekte/risc-v/freedom/rocket-chip/firrtl/utils/bin/firrtl.jar] Error 2

The file sbt-launch.jar does exist. We clone the repository with all sub-modules recusively. So all required data should be there.
We are using a cygwin terminal on a Windows 10 machine.
Did someone see this error? Any recommendation? Addtional information required?

Thanks
Stephan

PS: not an expert in using make

when executing
$ make -f Makefile.e300artydevkit verilog
following error is shown up.

Hi all,

I'm trying to understand what happens during the boot inside u500vc707 system.

I know that the Rocket core starts execution at address 0x1000, where there is the BootROM. I also know that the BootROM is generated from file freedom/bootrom/u500vc707devkit.img. In the same folder bootrom, I found file xip/xip.S.

Executing xip.S, the program counter at a certain point performs a jump to address XIP_TARGET_ADDR (#L19), but I don't find this constant defined in the entire repo.

Hence, can you please give me some more information? I fear I am missing something...

Thank you all!

Hi again!
I wonder if it is possible to run simple bare metal test on the system you provide. I think so (it is able to boot Linux!), hence I'm trying to find a way.

I find myself a bit confused, since actually there is a lot of material, like inside riscv-tools repo. For example riscv-tests, or also riscv-benchmarks. Despite this, it is not clear to me if they are related to the new untethered Rocket Chip, or to the old tethered one. Sometimes, since their last update is prior to the untether, I fear they are not good for me.

Can please tell me how to do bare metal tests? Or, if you prefer, pointing me to a repo or somewhere I can understand by myself how to do them?

Thank you so much again!

The Apache license is long and restrictive.
In particular, Section 4, subsections 2 and 4 both put completely unneeded restraints on the licensee.
It also is incompatible with older versions of the GPL.

Most RISCV projects use MIT.
Please consider choosing a more free license.

Thank you

Hi,

I'm trying to modify your U500 platform. In particular, my aim is to get the system clock not from the PCIe (I don't have this device), but deriving it from the MIG output clock.

My question is: which clock frequency do you give to the system? I mean the one of the top_clock signal, inside the U500VC707DevKitTop component.

Thank you so much!

The current E300 build succeeds, but doesn't work when flashed to the Arty. Flashing using vivado succeeds without error. Yet, when the Prog button is pushed, the image doesn't work as intended.

Flashing the 1-0-2 MCS file cited in the Getting Started documentation results in a working E-Series image. So, it doesn't seem to be an issue with the Arty, Vivado, or the flashing process.

Thanks,
D

i run into this error when i generate the verilog code

I noticed that the default FreedomUVC707Config use 4 big cores, in src/main/scala/unleashed/u500vc707devkit/Config.scala

class FreedomUVC707Config extends Config(
new WithJtagDTM ++
new WithNMemoryChannels(1) ++
new WithNBigCores(4) ++
new BaseConfig
)

so what should i do if i want to use only one big core? I tried to modify

new WithNBigCores(4) ++

to

new WithNBigCores(1) ++

but it failed to boot. What else need to be modified??

Thanks

Hi SiFive's expert,

$ make -f Makefile.e300artydevkit verilog

When I adding generated verilog code to Vivado 2016.4 and synthesis it encounter error ,please tell me how to fix it. Thanks~

Hi. I'm trying to boot linux on VC707 without an FMC Card..
How did you fix the system clock in scala?.?

Hi all,

I noticed that, apparently, moving from TileLink "made" with package tilelink and then with package tilelink2, you also changed the implementation!

A part from adding stuff like TLWidthWidget, TLAtomicAutomata etc, if now I have a look at TileLink buses inside the verilog output from your design in this repo, I don't see any of the stuff described in the overview of the TileLink Protocol.

I saw that now there are other "channels", called a, b, c, d and e; I suppose they replace the old Acquire, Probe, Release, Grant and Finish channels. A part from that, also the signals they use are different from the one of the overview.

What I want to ask you is this: is available some documentation about TileLink2? If not, how much does it change from "TileLink1", in the protocol, the channel aims...

Everything can be useful! Thank you so much!

I am having a whole lot of trouble finding a working combination of hardware and SD card image for the u500 on a VC707. By way of a sanity check, I am trying to get vanilla hardware and software to boot.

I have in the past successfully done this with older versions of the repository.

I have tried the following hardware:

• latest, Aug 20 hardware built with vivado 2016.4
• pre-built MCS linked in the u500 vcu707 guide.

And the following software

• some older vanilla freedom-u-sdk I had on an SD from a few months ago
• Unmodified build of the latest, Dec 2 freedom-u-sdk, master branch.
• Unmodified build of the latest, Jun 27 freedom-u-sdk, priv-1.10 branch.

In all cases, the result is the same: the bootloader runs, but fails to boot linux:

INIT
CMD0
CMD8
ACMD41
CMD58
CMD16
CMD18
LOADING  
BOOT

followed by nothing. I suspect some sort of disagreement between the priv ABI enforced by hardware, and expected by software.

These builds take a long time; any pointers would be greatly appreciated.
Is there a pre-built, known-good SD card image somewhere? This would sure help reduce the search space for this issue. Please advise.

Thanks in advance,
-ilia

Hi all! I'm trying to modify the u500vc707devkit project, removing the XilinxPCieX1 component. I worked on the Chisel code: in a few words, from Top.scala I removed all the stuff related to XilinxPCieX1. Then, I modified trait RocketPlexMaster, making it extends TopNetwork instead of L2Crossbar.

When I give command make -f Makefile.u500vc707devkit verilog, the verilog is produced, but I obtain an error. As you can see from the log (reported below), it doesn't say anything meaningful about what happened (or maybe I'm not able to see it!). Only an "Error 1" at the end.

My question is: is there a way to understand what happened? Maybe something like more output on screen, using an option via command line.

Thanks!

ERROR LOG:

mkdir -p /home/marco/repo/freedom/builds/u500vc707devkit/
java -jar /home/marco/repo/freedom/rocket-chip/sbt-launch.jar "run-main rocketchip.Generator /home/marco/repo/freedom/builds/u500vc707devkit sifive.freedom.unleashed.u500vc707devkit U500VC707DevKitTop sifive.freedom.unleashed.u500vc707devkit U500VC707DevKitConfig"
[info] Loading project definition from /home/marco/repo/freedom/rocket-chip/project
Using addons:
[info] Set current project to freedom (in build file:/home/marco/repo/freedom/)
[info] Compiling 1 Scala source to /home/marco/repo/freedom/rocket-chip/chisel3/target/scala-2.11/classes...
[info] Compiling 1 Scala source to /home/marco/repo/freedom/target/scala-2.11/classes...
[info] Running rocketchip.Generator /home/marco/repo/freedom/builds/u500vc707devkit sifive.freedom.unleashed.u500vc707devkit U500VC707DevKitTop sifive.freedom.unleashed.u500vc707devkit U500VC707DevKitConfig
[info] [0.002] Elaborating design...

Interrupt map:
[1, 1] => uart0
[2, 2] => spi0
[3, 6] => gpio

Generated Address Map
xilinxvc707mig 80000000 - 90000000, RWX [C]
uart0 54000000 - 54001000, RW
spi0 54001000 - 54002000, RW
bootrom 1000 - 2000, RX
debug 0 - 1000, RWX
gpio 54002000 - 54003000, RW
clint 2000000 - 2010000, RW
plic c000000 - 10000000, RW

Generated Configuration String
platform {
vendor ucb;
arch spike;
};
plic {
interface "plic";
ndevs 9;
priority { mem { 0x0c000000 0x0c00ffff; }; };
pending { mem { 0x0c001000 0x0c00107f; }; };
0 {
0 {
m {
ie { mem { 0x0c002000 0x0c00207f; }; };
ctl { mem { 0x0c200000 0x0c200007; }; };
};
s {
ie { mem { 0x0c002080 0x0c0020ff; }; };
ctl { mem { 0x0c201000 0x0c201007; }; };
};
};
};
};
leds {
interface "gpio";
ngpio 4;
mem { 0x54002000 0x54002003; };
};
rtc {
addr 0x200bff8;
};
ram {
0 {
addr 0x80000000;
size 0x10000000;
};
};
uart {
addr 0x54000000;
};
core {
0 {
0 {
isa rv64ima;
timecmp 0x02004000;
ipi 0x02000000;
};
};
};

[info] [6.936] Done elaborating.
[success] Total time: 21 s, completed Jan 21, 2017 7:58:29 PM
java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp /home/marco/repo/freedom/rocket-chip/firrtl/utils/bin/firrtl.jar firrtl.Driver -i /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.fir -o /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v -X verilog
sed -i -s "s/ output(.)__inout(.*)/inout \1__inout\2/g" /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && grep -q -F " .io_xilinxvc707mig__inout_ddr3_dq(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dq)," /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && sed -i -s "s/ .io_xilinxvc707mig__inout_ddr3_dq(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dq),/ .io_xilinxvc707mig__inout_ddr3_dq(io_xilinxvc707mig__inout_ddr3_dq),/g" /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && grep -q -F " .io_xilinxvc707mig__inout_ddr3_dqs_n(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_n)," /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && sed -i -s "s/ .io_xilinxvc707mig__inout_ddr3_dqs_n(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_n),/ .io_xilinxvc707mig__inout_ddr3_dqs_n(io_xilinxvc707mig__inout_ddr3_dqs_n),/g" /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && grep -q -F " .io_xilinxvc707mig__inout_ddr3_dqs_p(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_p)," /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && sed -i -s "s/ .io_xilinxvc707mig__inout_ddr3_dqs_p(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_p),/ .io_xilinxvc707mig__inout_ddr3_dqs_p(io_xilinxvc707mig__inout_ddr3_dqs_p),/g" /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && grep -q -F " .io_port__inout_ddr3_dq(xilinxvc707mig_io_port__inout_ddr3_dq)," /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && sed -i -s "s/ .io_port__inout_ddr3_dq(xilinxvc707mig_io_port__inout_ddr3_dq),/ .io_port__inout_ddr3_dq(io_xilinxvc707mig__inout_ddr3_dq),/g" /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && grep -q -F " .io_port__inout_ddr3_dqs_n(xilinxvc707mig_io_port__inout_ddr3_dqs_n)," /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && sed -i -s "s/ .io_port__inout_ddr3_dqs_n(xilinxvc707mig_io_port__inout_ddr3_dqs_n),/ .io_port__inout_ddr3_dqs_n(io_xilinxvc707mig__inout_ddr3_dqs_n),/g" /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && grep -q -F " .io_port__inout_ddr3_dqs_p(xilinxvc707mig_io_port__inout_ddr3_dqs_p)" /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && sed -i -s "s/ .io_port__inout_ddr3_dqs_p(xilinxvc707mig_io_port__inout_ddr3_dqs_p)/ .io_port__inout_ddr3_dqs_p(io_xilinxvc707mig__inout_ddr3_dqs_p)/g" /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && grep -q -F " .ddr3_dq(blackbox_ddr3_dq)," /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && sed -i -s "s/ .ddr3_dq(blackbox_ddr3_dq),/ .ddr3_dq(io_port__inout_ddr3_dq),/g" /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && grep -q -F " .ddr3_dqs_n(blackbox_ddr3_dqs_n)," /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && sed -i -s "s/ .ddr3_dqs_n(blackbox_ddr3_dqs_n),/ .ddr3_dqs_n(io_port__inout_ddr3_dqs_n),/g" /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && grep -q -F " .ddr3_dqs_p(blackbox_ddr3_dqs_p)," /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v && sed -i -s "s/ .ddr3_dqs_p(blackbox_ddr3_dqs_p),/ .ddr3_dqs_p(io_port__inout_ddr3_dqs_p),/g" /home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v
make: *** [/home/marco/repo/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.v] Error 1

Hi all,

I'd like to ask something about the UART in the U500 platform. In particular:

1. At which clock does it operate? Think about the process inside file:
   freedom/fpga/u500vc707devkit/src/system.v
   It is clocked using signal top_clock. Which is its frequency?

2. How do we have to set Minicom, to communicate with the vc707 FPGA?
   In your "SiFive-U500-vc707-gettingstarted-v0.2" guide, there are many parameters, like "Stop bits = 1".
   But if I look inside file:
   freedom/sifive-blocks/src/main/scala/devices/uart/UART.scala
   I see: stopBits: Int = 2,
   So, I am a bit confused! Which are the actual parameters?

Thank you for everything!

i click the link and it jump to the same address where the start guide is
and i cant find the“ configration memory file（.mcs）” download link

Hi I am evaluating various RISCV Cores. I am getting the following results for Sifive E31 & E51.

Is these results are correct or not? Can you share these information to me.
I want to change the cache memory size for Sifive Cores. So can you share how to change the cache memory for E31 & E51.

this error happened when i generate the mcs file
i have compile the toolchain once in the rock-chip just follow the commands in this link https://github.com/freechipsproject/rocket-chip#setting-up-the-riscv-environment-variable
do i have to compile again in the /freedom/rocket-chip/riscv-tools or i can use the former generated toolchain,if so where can i find it.
by the way,i used to compile the riscv-toolchain use the command: ./build-rv32ima.sh does this means i generate a file named riscv-32-unknown-elf-gcc.but what i need is riscv-64-unknown-elf-gcc.

I was studying into the TLv1.7 spec and the implementation/API spec (https://docs.google.com/document/d/1vBPgrlvuLmvCB33dVb1wr3xc9f8uOrNzZ9AFMGHeSkg/pub).
I understand that the L1 cache level would be a Master agent (using ClientMetadata APIs) and the L2 would be a Slave agent (using ManagerMetadata APIs) that holds the directory.

1. Is this above understanding correct?

However I don't seem to find the implementation of the class ManagerMetadata anywhere in the repository.
2. Is it present somewhere/other branch?
3. If yes, Can you direct me to the file that implements this?

4. If no, How is coherency handled in the current situation without ManagerMetadata? Do we have multiple cores or just a single core of the rocketchip supported in the current repository for U500 Freedom SoC? Any specific files/directory you can direct me to would be great.

Thank you.
Saurabh

@palmer-dabbelt
When I run "make -f Makefile.u500vc707devkit mcs", the following error is displayed.
"make verilog" succeeded without errors.

ERROR: [Board 49-71] The board_part definition was not found for xilinx.com:vc707:part0:1.3. The project's board_part property was not set, but the project's part property was set to xc7vx485tffg1761-2. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.

Hi when I am trying to execute make -f Makefile.e300artydevkit mcs targets in Freedom E 310, i am getting the following error how to i am resolve this issue.....

export_ip_user_files -of_objects $obj -no_script -force

invalid command name "export_ip_user_files"
while executing
"export_ip_user_files -of_objects $obj -no_script -force"
(file "script/init.tcl" line 36)
INFO: [Common 17-206] Exiting Vivado at Thu May 12 10:42:37 2016...
make[1]: *** [obj/system.bit] Error 1

Hi all,

is it possible to modify the internal CPU parallelism? (i.e. the Rocket Core one) I looked at the Chisel code, but I'm not sure if I understood right.
Is it possible to switch between a 32 bits and a 64 bits (and 128 bits) CPU? In other words: is the Rocket-Chip architecture able to implement all the RV32, RV64 (and RV128) RISC-V ISAs?

If yes, is there a configuration parameter able to do that "automatically"? Or do I have to modify something by hand?

Thank you so much!

Hi all,

I'm studying the address map of the u500vc707devkit. My question is about the Object ConfigStringOutput, which you define inside freedom/src/main/scala/unleashed/u500vc707devkit/Top.scala#L45, but here is also a default one created in sifive/rocket-chip/src/main/scala/coreplex/RISCVPlatform.scala#L33.

I wonder if it is only a sort of "graphical feedback" (since, when you compile the Chip, you have output on video) or it is involved to set the the address map, TileLink or Rocket processor...

Can you please also clarify the aim of strings globalConfigString and hartConfigStrings, which you can find in TLPLIC or CoreplexLocalInterrupter?

Thank you so much!

Any chance you could commit a Makefile.u500artydevkit? I have an Arty board that I've been using as a U500. Thanks.

Hi all,

I want to know why Freedom E300 no date cache ? what the purpose this design.

Hi all,

studying your repo, I understood that probably in your system (given by the configuration inside U500VC707DevKitConfig) you:

• do not use L2 cache (I didn't find as included any of the WithL2Cache configs or similar)
• do not use FPU (you include configs WithoutFPU; then I also had a look at how its parameters as used by tile.scala and rocket.scala)

Am I correct? If not, can you please tell me where you add those components?

Thank you all!

Hi,

when i make verilog of U500 for FPGA, got the following error:

[info] Compiling 57 Scala sources to /root/freedom/sifive-blocks/target/scala-2.11/classes ...
[error] /root/freedom/sifive-blocks/src/main/scala/devices/chiplink/SourceC.scala:75:13: value error is not a member of freechips.rocketchip.tilelink.TLBundleC
[error] io.c.bits.error := Bool(false) // !!! need a packet footer
[error] ^
[error] /root/freedom/sifive-blocks/src/main/scala/devices/chiplink/SourceD.scala:71:13: value error is not a member of freechips.rocketchip.tilelink.TLBundleD
[error] io.d.bits.error := Bool(false) // !!! frack => need packet footer?
[error] ^
[error] /root/freedom/sifive-blocks/src/main/scala/devices/mockaon/MockAONPeriphery.scala:7:8: object HasPeripheryCLINT is not a member of package freechips.rocketchip.devices.tilelink
[error] import freechips.rocketchip.devices.tilelink.HasPeripheryCLINT
[error] ^
[error] /root/freedom/sifive-blocks/src/main/scala/devices/mockaon/MockAONPeriphery.scala:16:35: not found: type HasPeripheryCLINT
[error] trait HasPeripheryMockAON extends HasPeripheryCLINT with HasPeripheryDebug { this: BaseSubsystem =>
[error] ^
[error] /root/freedom/sifive-blocks/src/main/scala/devices/mockaon/MockAONPeriphery.scala:48:9: value clint is not a member of sifive.blocks.devices.mockaon.HasPeripheryMockAON
[error] outer.clint.module.io.rtcTick := rtc_tick
[error] ^
[error] 5 errors found
[error] (sifiveBlocks / Compile / compileIncremental) Compilation failed
[error] Total time: 59 s, completed 2018-5-30 22:12:27
make: *** [/root/freedom/builds/u500vc707devkit/sifive.freedom.unleashed.u500vc707devkit.U500VC707DevKitConfig.fir] Error 1

The related class from my local after i git clone and checkout the whole project:

final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(width = 3)
val param = UInt(width = TLPermissions.cWidth) // shrink or report perms
val size = UInt(width = params.sizeBits)
val source = UInt(width = params.sourceBits) // from
val address = UInt(width = params.addressBits) // to
// variable fields during multibeat:
val data = UInt(width = params.dataBits)
val corrupt = Bool() // only applies to *Data messages
}

final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(width = 3)
val param = UInt(width = TLPermissions.bdWidth) // cap perms
val size = UInt(width = params.sizeBits)
val source = UInt(width = params.sourceBits) // to
val sink = UInt(width = params.sinkBits) // from
val denied = Bool() // implies corrupt iff *Data
// variable fields during multibeat:
val data = UInt(width = params.dataBits)
val corrupt = Bool() // only applies to *Data messages
}

For the first/second error, actually, the class TLBundleC/TLBundleD doesn't contain the member of error.

i just did the following step:
$ git clone https://github.com/sifive/freedom.git
$ git submodule update --init
$ cd rocket-chip
$ git submodule update --init

The related class in github repo:

final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(width = 3)
val param = UInt(width = TLPermissions.cWidth) // shrink or report perms
val size = UInt(width = params.sizeBits)
val source = UInt(width = params.sourceBits) // from
val address = UInt(width = params.addressBits) // to
// variable fields during multibeat:
val data = UInt(width = params.dataBits)
val error = Bool() // AccessAck[Data]
}

final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(width = 3)
val param = UInt(width = TLPermissions.bdWidth) // cap perms
val size = UInt(width = params.sizeBits)
val source = UInt(width = params.sourceBits) // to
val sink = UInt(width = params.sinkBits) // from
// variable fields during multibeat:
val data = UInt(width = params.dataBits)
val error = Bool() // AccessAck[Data], Grant[Data]
}
---------------------------------------------------------------------------------------------------------- it contains the member of error indeedly!!!!

why they are mismatched ???

Thanks a lot

It worked a couple of weeks ago, but now I (and a colleague) get this error message:

Cloning into 'env'...
fatal: read error: Operation timed out
fatal: clone of 'git://github.com/ucb-bar/riscv-test-env.git' into submodule path 'env' failed

Hi,

when i make verilog for FPGA platform, got the fllowing error:

make -C /mnt/hgfs/SharedDir/freedom/rocket-chip/firrtl SBT="java -jar /mnt/hgfs/SharedDir/freedom/rocket-chip/sbt-launch.jar" root_dir=/mnt/hgfs/SharedDir/freedom/rocket-chip/firrtl build-scala
make[1]: Entering directory /mnt/hgfs/SharedDir/freedom/rocket-chip/firrtl' java -jar /mnt/hgfs/SharedDir/freedom/rocket-chip/sbt-launch.jar "assembly" [info] Loading settings from plugins.sbt ... [info] Loading project definition from /mnt/hgfs/SharedDir/freedom/rocket-chip/firrtl/project [info] Loading settings from build.sbt ... [info] Set current project to firrtl (in build file:/mnt/hgfs/SharedDir/freedom/rocket-chip/firrtl/) [info] Updating ... [info] Done updating. [error] java.io.FileNotFoundException: /mnt/hgfs/SharedDir/freedom/rocket-chip/firrtl/target/streams/$global/assemblyOption/$global/streams/assembly/c25a67d8a2a44bb463d039a0572114b81c8c0d54_dir/firrtl/passes/CommonSubexpressionElimination$$anonfun$firrtl$passes$CommonSubexpressionElimination$$eliminateNodeRef$1$1.class (File name too long) [error] at java.io.FileOutputStream.open0(Native Method) [error] at java.io.FileOutputStream.open(FileOutputStream.java:270) [error] at java.io.FileOutputStream.<init>(FileOutputStream.java:213) [error] at java.io.FileOutputStream.<init>(FileOutputStream.java:162) [error] at sbt.io.Using$.$anonfun$fileOutputChannel$1(Using.scala:93) [error] at sbt.io.Using$$anon$2.openImpl(Using.scala:76) [error] at sbt.io.OpenFile.open(Using.scala:43) [error] at sbt.io.OpenFile.open$(Using.scala:39) [error] at sbt.io.Using$$anon$2.open(Using.scala:75) [error] at sbt.io.Using$$anon$2.open(Using.scala:75) [error] at sbt.io.Using.apply(Using.scala:21) [error] at sbt.io.IO$.$anonfun$copyFile$3(IO.scala:714) [error] at sbt.io.IO$.$anonfun$copyFile$3$adapted(IO.scala:713) [error] at sbt.io.Using.apply(Using.scala:22) [error] at sbt.io.IO$.copyFile(IO.scala:713) [error] at sbt.io.IO$.copyImpl(IO.scala:651) [error] at sbt.io.IO$.$anonfun$copy$1(IO.scala:639) [error] at scala.Function$.$anonfun$tupled$1(Function.scala:77) [error] at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:234) [error] at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:59) [error] at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:52) [error] at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48) [error] at scala.collection.TraversableLike.map(TraversableLike.scala:234) [error] at scala.collection.TraversableLike.map$(TraversableLike.scala:227) [error] at scala.collection.AbstractTraversable.map(Traversable.scala:104) [error] at sbt.io.IO$.copy(IO.scala:639) [error] at sbt.io.IO$.copyDirectory(IO.scala:685) [error] at sbt.io.IO$.copyDirectory(IO.scala:674) [error] at sbt.io.IO$.copyDirectory(IO.scala:657) [error] at sbtassembly.Assembly$.$anonfun$assembleMappings$8(Assembly.scala:194) [error] at scala.collection.parallel.AugmentedIterableIterator.map2combiner(RemainsIterator.scala:112) [error] at scala.collection.parallel.AugmentedIterableIterator.map2combiner$(RemainsIterator.scala:109) [error] at scala.collection.parallel.immutable.ParVector$ParVectorIterator.map2combiner(ParVector.scala:62) [error] at scala.collection.parallel.ParIterableLike$Map.leaf(ParIterableLike.scala:1052) [error] at scala.collection.parallel.Task.$anonfun$tryLeaf$1(Tasks.scala:49) [error] at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:12) [error] at scala.util.control.Breaks$$anon$1.catchBreak(Breaks.scala:63) [error] at scala.collection.parallel.Task.tryLeaf(Tasks.scala:52) [error] at scala.collection.parallel.Task.tryLeaf$(Tasks.scala:46) [error] at scala.collection.parallel.ParIterableLike$Map.tryLeaf(ParIterableLike.scala:1049) [error] at scala.collection.parallel.AdaptiveWorkStealingTasks$WrappedTask.compute(Tasks.scala:149) [error] at scala.collection.parallel.AdaptiveWorkStealingTasks$WrappedTask.compute$(Tasks.scala:145) [error] at scala.collection.parallel.AdaptiveWorkStealingForkJoinTasks$WrappedTask.compute(Tasks.scala:440) [error] at java.util.concurrent.RecursiveAction.exec(RecursiveAction.java:189) [error] at java.util.concurrent.ForkJoinTask.doExec(ForkJoinTask.java:289) [error] at java.util.concurrent.ForkJoinTask.doJoin(ForkJoinTask.java:389) [error] at java.util.concurrent.ForkJoinTask.join(ForkJoinTask.java:719) [error] at scala.collection.parallel.ForkJoinTasks$WrappedTask.sync(Tasks.scala:375) [error] at scala.collection.parallel.ForkJoinTasks$WrappedTask.sync$(Tasks.scala:375) [error] at scala.collection.parallel.AdaptiveWorkStealingForkJoinTasks$WrappedTask.sync(Tasks.scala:440) [error] at scala.collection.parallel.ForkJoinTasks.executeAndWaitResult(Tasks.scala:423) [error] at scala.collection.parallel.ForkJoinTasks.executeAndWaitResult$(Tasks.scala:414) [error] at scala.collection.parallel.ForkJoinTaskSupport.executeAndWaitResult(TaskSupport.scala:56) [error] at scala.collection.parallel.ExecutionContextTasks.executeAndWaitResult(Tasks.scala:555) [error] at scala.collection.parallel.ExecutionContextTasks.executeAndWaitResult$(Tasks.scala:555) [error] at scala.collection.parallel.ExecutionContextTaskSupport.executeAndWaitResult(TaskSupport.scala:80) [error] at scala.collection.parallel.ParIterableLike$ResultMapping.leaf(ParIterableLike.scala:956) [error] at scala.collection.parallel.Task.$anonfun$tryLeaf$1(Tasks.scala:49) [error] at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:12) [error] at scala.util.control.Breaks$$anon$1.catchBreak(Breaks.scala:63) [error] at scala.collection.parallel.Task.tryLeaf(Tasks.scala:52) [error] at scala.collection.parallel.Task.tryLeaf$(Tasks.scala:46) [error] at scala.collection.parallel.ParIterableLike$ResultMapping.tryLeaf(ParIterableLike.scala:951) [error] at scala.collection.parallel.AdaptiveWorkStealingTasks$WrappedTask.compute(Tasks.scala:149) [error] at scala.collection.parallel.AdaptiveWorkStealingTasks$WrappedTask.compute$(Tasks.scala:145) [error] at scala.collection.parallel.AdaptiveWorkStealingForkJoinTasks$WrappedTask.compute(Tasks.scala:440) [error] at java.util.concurrent.RecursiveAction.exec(RecursiveAction.java:189) [error] at java.util.concurrent.ForkJoinTask.doExec(ForkJoinTask.java:289) [error] at java.util.concurrent.ForkJoinPool$WorkQueue.runTask(ForkJoinPool.java:1056) [error] at java.util.concurrent.ForkJoinPool.runWorker(ForkJoinPool.java:1692) [error] at java.util.concurrent.ForkJoinWorkerThread.run(ForkJoinWorkerThread.java:157) [error] (assembly / assembledMappings) java.io.FileNotFoundException: /mnt/hgfs/SharedDir/freedom/rocket-chip/firrtl/target/streams/$global/assemblyOption/$global/streams/assembly/c25a67d8a2a44bb463d039a0572114b81c8c0d54_dir/firrtl/passes/CommonSubexpressionElimination$$anonfun$firrtl$passes$CommonSubexpressionElimination$$eliminateNodeRef$1$1.class (File name too long) [error] Total time: 30 s, completed 2018-5-29 15:03:48 make[1]: *** [/mnt/hgfs/SharedDir/freedom/rocket-chip/firrtl/utils/bin/firrtl.jar] Error 1 make[1]: Leaving directory /mnt/hgfs/SharedDir/freedom/rocket-chip/firrtl'
make: *** [/mnt/hgfs/SharedDir/freedom/rocket-chip/firrtl/utils/bin/firrtl.jar] Error 2

Thanks a lot for your help

Shouldn't we add links to the Getting Started Guides and Platform Specs? I think that will give people a deeper understanding of what they're looking at in this repo.

Hi,

I noticed that the repo has been updated recently and a pull request is accepted, and the flow of generating mcs for Arty board is broken.

What I did:

git clone --recursive https://github.com/sifive/freedom.git
cd freedom
make -f Makefile.e300artydevkit verilog (as per README) - this generates verilog without error.
make -f Makefile.e300artydevkit mcs (as per README) - this prompts an error below:

"

make -C /home/ken/freedom/bootrom/xip romgen
make[1]: Entering directory '/home/ken/freedom/bootrom/xip'
dtc -I dts -O dtb -o /home/ken/freedom/builds/e300artydevkit/E300ArtyDevKitConfig.dtb /home/ken/freedom/builds/e300artydevkit/E300ArtyDevKitConfig.dts
/bin/riscv64-unknown-elf-gcc -march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"/home/ken/freedom/builds/e300artydevkit/E300ArtyDevKitConfig.dtb"' -static -nostdlib -o /home/ken/freedom/builds/e300artydevkit/xip.elf xip.S
make[1]: /bin/riscv64-unknown-elf-gcc: Command not found
Makefile:17: recipe for target '/home/ken/freedom/builds/e300artydevkit/xip.elf' failed
make[1]: *** [/home/ken/freedom/builds/e300artydevkit/xip.elf] Error 127
make[1]: Leaving directory '/home/ken/freedom/bootrom/xip'
common.mk:68: recipe for target '/home/ken/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.rom.v' failed
make: *** [/home/ken/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.rom.v] Error 2

"

Is this intentional? How could I resolve this? Thanks.

Hi,

when i make verilog of U500 FPGA, got the following errors:

[error] /root/freedom/sifive-blocks/src/main/scala/devices/mockaon/MockAONPeriphery.scala:7:8: object HasPeripheryCLINT is not a member of package freechips.rocketchip.devices.tilelink
[error] import freechips.rocketchip.devices.tilelink.HasPeripheryCLINT
[error] ^
[error] /root/freedom/sifive-blocks/src/main/scala/devices/mockaon/MockAONPeriphery.scala:16:35: not found: type HasPeripheryCLINT
[error] trait HasPeripheryMockAON extends HasPeripheryCLINT with HasPeripheryDebug { this: BaseSubsystem =>
[error] ^

And i also can't found the object HasPeripheryCLINT in my clone project, but it exist at github repo of latest version (rocket-chip/src/main/scala/devices/tilelink/CLINT.scala), why I can't get the CLINT.scala with "HasPeripheryCLINT" ???

Thanks a lot

Hi,all
I'm use command make upload PROGRAM=hello BOARD=freedom-e300-arty in the freedon-e-sdk directory. so,you can tell me the why?

hi,all

cd freedom/fpga/e300artydevkit
make

hi,all

when i use this command to generted verilog code, met jvm error! please help me~thanks.

Hi,
I have generated the verilog RTL for the Freedom E300 Chip. I would like to run an application on this RTL.
Is there a testbench available that would take the application as input and run it on the RTL? If so, where can I find it?

Regards,
Akhilesh Iyer.

Hi all,
I want to how add another UART device to U500VC707DevKitSystem.
I know there is a PeripheryUART in U500 code, which the addr is 0x54000000.
If I want to add another UART device, do I need to implement the another PeripheryUART at device directory, which connect to peripheryBus? Or, I only need with one more PeripheryUART in U500VC707DevKitSystem?
Everything can be useful! Thank you so much!

Hi I am trying to synthesize the arty bitstream but I am getting an error. Any suggestions?

% make -f Makefile.e300artydevkit mcs    
VSRC_TOP=/media/esdentem/Venture_Data/projects/riscv/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.v EXTRA_VSRCS="/media/esdentem/Venture_Data/projects/riscv/freedom/rocket-chip/vsrc/AsyncResetReg.v /media/esdentem/Venture_Data/projects/riscv/freedom/rocket-chip/vsrc/DebugTransportModuleJtag.v /media/esdentem/Venture_Data/projects/riscv/freedom/sifive-blocks/vsrc/SRLatch.v" make -C /media/esdentem/Venture_Data/projects/riscv/freedom/fpga/e300artydevkit mcs
make[1]: Entering directory '/media/esdentem/Venture_Data/projects/riscv/freedom/fpga/e300artydevkit'
VSRC_TOP=/media/esdentem/Venture_Data/projects/riscv/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.v EXTRA_VSRCS="/media/esdentem/Venture_Data/projects/riscv/freedom/rocket-chip/vsrc/AsyncResetReg.v /media/esdentem/Venture_Data/projects/riscv/freedom/rocket-chip/vsrc/DebugTransportModuleJtag.v /media/esdentem/Venture_Data/projects/riscv/freedom/sifive-blocks/vsrc/SRLatch.v" vivado -nojournal -mode batch -source script/board.tcl -source script/prologue.tcl -source script/init.tcl -source script/impl.tcl
awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub

****** Vivado v2016.4 (64-bit)
  **** SW Build 1756540 on Mon Jan 23 19:11:19 MST 2017
  **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source script/board.tcl
# set name {arty_e300devkit}
# set part_fpga {xc7a35ticsg324-1L}
# set part_board {digilentinc.com:arty:part0:1.1}
# set bootrom_inst {rom}
source script/prologue.tcl
# set scriptdir [file dirname [info script]]
# set commondir [file dirname $scriptdir]
# set srcdir [file join $commondir src]
# set constrsdir [file join $commondir constrs]
# set wrkdir [file join [pwd] obj]
# set ipdir [file join $wrkdir ip]
# set top {system}
# create_project -part $part_fpga -in_memory
# set_property -dict [list \
#   BOARD_PART $part_board \
#   TARGET_LANGUAGE {Verilog} \
#   SIMULATOR_LANGUAGE {Mixed} \
#   TARGET_SIMULATOR {XSim} \
#   DEFAULT_LIB {xil_defaultlib} \
#   IP_REPO_PATHS $ipdir \
#   ] [current_project]
ERROR: [Board 49-71] The board_part definition was not found for digilentinc.com:arty:part0:1.1. The project's board_part property was not set, but the project's part property was set to xc7a35ticsg324-1L. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.
INFO: [Common 17-17] undo 'set_property'

    while executing
"rdi::add_properties -dict {BOARD_PART digilentinc.com:arty:part0:1.1 TARGET_LANGUAGE Verilog SIMULATOR_LANGUAGE Mixed TARGET_SIMULATOR XSim DEFAULT_LI..."
    invoked from within
"set_property -dict [list \
  BOARD_PART $part_board \
  TARGET_LANGUAGE {Verilog} \
  SIMULATOR_LANGUAGE {Mixed} \
  TARGET_SIMULATOR {XSim} \
  DEFAU..."
    (file "script/prologue.tcl" line 12)
INFO: [Common 17-206] Exiting Vivado at Sun Mar 12 15:54:17 2017...
Makefile:13: recipe for target 'obj/system.bit' failed
make[1]: *** [obj/system.bit] Error 1
make[1]: Leaving directory '/media/esdentem/Venture_Data/projects/riscv/freedom/fpga/e300artydevkit'
common.mk:55: recipe for target '/media/esdentem/Venture_Data/projects/riscv/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.mcs' failed
make: *** [/media/esdentem/Venture_Data/projects/riscv/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.mcs] Error 2
make -f Makefile.e300artydevkit mcs  6.51s user 0.12s system 49% cpu 13.299 total

Let me know if you need more information.

Hi,all

At first, I want to know if the generated verilog code by command $ make -f Makefile.e300artydevkit verilog just is RISC-V core not contain demo program ?

Then, my fpga image contain fpga configuration file and demo program , so when I upload the program into board by freedom-e-sdk occur some errors , whether there is relationship with that ?

Finally,I want to generate verilog according the command of $ make -f Makefile.e300artydevkit verilog . But, after generated verilog code add to vivado 2016.4 , when "run synthesis" occured some error.The prompt message is "module AsyncResetReg not found",I don't konw how to solve it , please tell me if you know. Thanks very much!

Hi, I am trying to use already present hardware accelerator in Rocket chip. To use it I am doing the following step:

1. In freedom/rocket-chip/src/main/scala/coreplex/Config.scala adding this
   class WithAccumRocc extends Config((site, here, up) => {
   case RocketTilesKey => up(RocketTilesKey, site) map { r =>
   r.copy(rocc =
   Seq(
   RoCCParams(
   opcodes = OpcodeSet.custom1,
   generator = (p: Parameters) => LazyModule(new CharacterCountExample()(p)))
   ))
   }
   })
2. In freedom/rocket-chip/src/main/scala/system/Config.scala adding this
   class TinyConfig extends Config(
   //add by me
   new WithAccumRocc ++
   new WithNMemoryChannels(0) ++
   new WithStatelessBridge ++
   new WithNTinyCores(1) ++
   new BaseConfig)
   Now when I built it in freedom using make -f Makefile.e300artydevkit verilog I am getting the following error:
   java -jar /home/anbuntu/freedom/rocket-chip/sbt-launch.jar "run-main freechips.rocketchip.system.Generator /home/anbuntu/freedom/builds/e300artydevkit sifive.freedom.everywhere.e300artydevkit E300ArtyDevKitFPGAChip sifive.freedom.everywhere.e300artydevkit E300ArtyDevKitConfig"
   [info] Loading project definition from /home/anbuntu/freedom/rocket-chip/project
   Using addons:
   [info] Set current project to freedom (in build file:/home/anbuntu/freedom/)
   [info] Compiling 1 Scala source to /home/anbuntu/freedom/rocket-chip/chisel3/target/scala-2.11/classes...
   [info] Packaging /home/anbuntu/freedom/rocket-chip/chisel3/target/scala-2.11/chisel3_2.11-3.1-SNAPSHOT.jar ...
   [info] Done packaging.
   [info] Compiling 1 Scala source to /home/anbuntu/freedom/rocket-chip/target/scala-2.11/classes...
   [info] Running freechips.rocketchip.system.Generator /home/anbuntu/freedom/builds/e300artydevkit sifive.freedom.everywhere.e300artydevkit E300ArtyDevKitFPGAChip sifive.freedom.everywhere.e300artydevkit E300ArtyDevKitConfig
   [info] [0.003] Elaborating design...
   Interrupt map (1 harts 52 interrupts):
   [1, 2] => aon
   [3, 3] => uarts_0
   [4, 4] => uarts_1
   [5, 5] => qspis_0
   [6, 6] => spis_0
   [7, 7] => spis_1
   [8, 39] => gpios_0
   [40, 43] => pwms_0
   [44, 47] => pwms_1
   [48, 51] => pwms_2
   [52, 52] => i2c_0

[error] (run-main-0) java.lang.reflect.InvocationTargetException
java.lang.reflect.InvocationTargetException
at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
at freechips.rocketchip.util.HasGeneratorUtilities$$anonfun$2.apply(GeneratorUtils.scala:50)
at freechips.rocketchip.util.HasGeneratorUtilities$$anonfun$2.apply(GeneratorUtils.scala:47)
at chisel3.core.Module$.do_apply(Module.scala:42)
at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:92)
at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:92)
at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:240)
at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:238)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
at chisel3.internal.Builder$.build(Builder.scala:238)
at chisel3.Driver$.elaborate(Driver.scala:92)
at freechips.rocketchip.util.HasGeneratorUtilities$class.elaborate(GeneratorUtils.scala:53)
at freechips.rocketchip.system.Generator$.elaborate(Generator.scala:12)
at freechips.rocketchip.util.GeneratorApp$class.circuit(GeneratorUtils.scala:100)
at freechips.rocketchip.system.Generator$.circuit$lzycompute(Generator.scala:12)
at freechips.rocketchip.system.Generator$.circuit(Generator.scala:12)
at freechips.rocketchip.util.GeneratorApp$class.generateFirrtl(GeneratorUtils.scala:106)
at freechips.rocketchip.system.Generator$.generateFirrtl(Generator.scala:12)
at freechips.rocketchip.system.Generator$.delayedEndpoint$freechips$rocketchip$system$Generator$1(Generator.scala:89)
at freechips.rocketchip.system.Generator$delayedInit$body.apply(Generator.scala:12)
at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
at scala.App$$anonfun$main$1.apply(App.scala:76)
at scala.App$$anonfun$main$1.apply(App.scala:76)
at scala.collection.immutable.List.foreach(List.scala:381)
at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
at scala.App$class.main(App.scala:76)
at freechips.rocketchip.system.Generator$.main(Generator.scala:12)
at freechips.rocketchip.system.Generator.main(Generator.scala)
at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.lang.reflect.Method.invoke(Method.java:498)
Caused by: scala.MatchError: null
at chisel3.core.Binding$.chisel3$core$Binding$$walkToBinding(Binding.scala:62)
at chisel3.core.Binding$.bind(Binding.scala:88)
at chisel3.core.BaseModule.IO(Module.scala:220)
at Chisel.package$CompatibilityModule.autoWrapPorts(compatibility.scala:186)
at chisel3.core.Binding$$anonfun$checkSynthesizable$1.apply(Binding.scala:125)
at chisel3.core.Binding$$anonfun$checkSynthesizable$1.apply(Binding.scala:121)
at chisel3.core.Binding$.chisel3$core$Binding$$walkToBinding(Binding.scala:63)
at chisel3.core.Binding$.checkSynthesizable(Binding.scala:119)
at chisel3.core.Bits.compop(Bits.scala:167)
at chisel3.core.UInt.do$eq$eq$eq(Bits.scala:482)
at freechips.rocketchip.tile.OpcodeSet$$anonfun$matches$1.apply(LazyRoCC.scala:363)
at freechips.rocketchip.tile.OpcodeSet$$anonfun$matches$1.apply(LazyRoCC.scala:363)
at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
at scala.collection.immutable.List.foreach(List.scala:381)
at scala.collection.TraversableLike$class.map(TraversableLike.scala:245)
at scala.collection.immutable.List.map(List.scala:285)
at freechips.rocketchip.tile.OpcodeSet.matches(LazyRoCC.scala:363)
at freechips.rocketchip.tile.RoccCommandRouter$$anonfun$41.apply(LazyRoCC.scala:384)
at freechips.rocketchip.tile.RoccCommandRouter$$anonfun$41.apply(LazyRoCC.scala:383)
at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
at scala.collection.Iterator$class.foreach(Iterator.scala:742)
at scala.collection.AbstractIterator.foreach(Iterator.scala:1194)
at scala.collection.IterableLike$class.foreach(IterableLike.scala:72)
at scala.collection.AbstractIterable.foreach(Iterable.scala:54)
at scala.collection.TraversableLike$class.map(TraversableLike.scala:245)
at scala.collection.AbstractTraversable.map(Traversable.scala:104)
at freechips.rocketchip.tile.RoccCommandRouter.(LazyRoCC.scala:383)
at freechips.rocketchip.tile.HasLazyRoCCModule$$anonfun$23.apply(LazyRoCC.scala:114)
at freechips.rocketchip.tile.HasLazyRoCCModule$$anonfun$23.apply(LazyRoCC.scala:114)
at chisel3.core.Module$.do_apply(Module.scala:42)
at freechips.rocketchip.tile.HasLazyRoCCModule$class.$init$(LazyRoCC.scala:114)
at freechips.rocketchip.tile.RocketTileModule.(RocketTile.scala:136)
at freechips.rocketchip.tile.RocketTile.module$lzycompute(RocketTile.scala:129)
at freechips.rocketchip.tile.RocketTile.module(RocketTile.scala:129)
at freechips.rocketchip.tile.RocketTile.module(RocketTile.scala:31)
at freechips.rocketchip.diplomacy.LazyModule$$anonfun$instantiate$1$$anonfun$apply$5.apply(LazyModule.scala:61)
at freechips.rocketchip.diplomacy.LazyModule$$anonfun$instantiate$1$$anonfun$apply$5.apply(LazyModule.scala:61)
at chisel3.core.Module$.do_apply(Module.scala:42)
at freechips.rocketchip.diplomacy.LazyModule$$anonfun$instantiate$1.apply(LazyModule.scala:61)
at freechips.rocketchip.diplomacy.LazyModule$$anonfun$instantiate$1.apply(LazyModule.scala:58)
at scala.collection.immutable.List.foreach(List.scala:381)
at freechips.rocketchip.diplomacy.LazyModule.instantiate(LazyModule.scala:58)
at freechips.rocketchip.diplomacy.LazyModuleImp.(LazyModule.scala:158)
at freechips.rocketchip.tile.RocketTileWrapper$$anon$5.(RocketTile.scala:203)
at freechips.rocketchip.tile.RocketTileWrapper.module$lzycompute(RocketTile.scala:203)
at freechips.rocketchip.tile.RocketTileWrapper.module(RocketTile.scala:203)
at freechips.rocketchip.tile.RocketTileWrapper.module(RocketTile.scala:172)
at freechips.rocketchip.diplomacy.LazyModule$$anonfun$instantiate$1$$anonfun$apply$5.apply(LazyModule.scala:61)
at freechips.rocketchip.diplomacy.LazyModule$$anonfun$instantiate$1$$anonfun$apply$5.apply(LazyModule.scala:61)
at chisel3.core.Module$.do_apply(Module.scala:42)
at freechips.rocketchip.diplomacy.LazyModule$$anonfun$instantiate$1.apply(LazyModule.scala:61)
at freechips.rocketchip.diplomacy.LazyModule$$anonfun$instantiate$1.apply(LazyModule.scala:58)
at scala.collection.immutable.List.foreach(List.scala:381)
at freechips.rocketchip.diplomacy.LazyModule.instantiate(LazyModule.scala:58)
at freechips.rocketchip.diplomacy.LazyMultiIOModuleImp.(LazyModule.scala:162)
at freechips.rocketchip.coreplex.BareCoreplexModule.(BaseCoreplex.scala:25)
at freechips.rocketchip.coreplex.BaseCoreplexModule.(BaseCoreplex.scala:91)
at freechips.rocketchip.coreplex.RocketCoreplexModule.(RocketCoreplex.scala:128)
at sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitSystemModule.(System.scala:39)
at sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitSystem.module$lzycompute(System.scala:35)
at sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitSystem.module(System.scala:35)
at sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitPlatform$$anonfun$4.apply(Platform.scala:55)
at sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitPlatform$$anonfun$4.apply(Platform.scala:55)
at chisel3.core.Module$.do_apply(Module.scala:42)
at sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitPlatform.(Platform.scala:55)
at sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitFPGAChip$$anonfun$2$$anonfun$3.apply(FPGAChip.scala:41)
at sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitFPGAChip$$anonfun$2$$anonfun$3.apply(FPGAChip.scala:41)
at chisel3.core.Module$.do_apply(Module.scala:42)
at sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitFPGAChip$$anonfun$2.apply$mcV$sp(FPGAChip.scala:41)
at sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitFPGAChip$$anonfun$2.apply(FPGAChip.scala:40)
at sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitFPGAChip$$anonfun$2.apply(FPGAChip.scala:40)
at chisel3.core.withClockAndReset$.apply(MultiClock.scala:26)
at sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitFPGAChip.(FPGAChip.scala:40)
at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
at freechips.rocketchip.util.HasGeneratorUtilities$$anonfun$2.apply(GeneratorUtils.scala:50)
at freechips.rocketchip.util.HasGeneratorUtilities$$anonfun$2.apply(GeneratorUtils.scala:47)
at chisel3.core.Module$.do_apply(Module.scala:42)
at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:92)
at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:92)
at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:240)
at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:238)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
at chisel3.internal.Builder$.build(Builder.scala:238)
at chisel3.Driver$.elaborate(Driver.scala:92)
at freechips.rocketchip.util.HasGeneratorUtilities$class.elaborate(GeneratorUtils.scala:53)
at freechips.rocketchip.system.Generator$.elaborate(Generator.scala:12)
at freechips.rocketchip.util.GeneratorApp$class.circuit(GeneratorUtils.scala:100)
at freechips.rocketchip.system.Generator$.circuit$lzycompute(Generator.scala:12)
at freechips.rocketchip.system.Generator$.circuit(Generator.scala:12)
at freechips.rocketchip.util.GeneratorApp$class.generateFirrtl(GeneratorUtils.scala:106)
at freechips.rocketchip.system.Generator$.generateFirrtl(Generator.scala:12)
at freechips.rocketchip.system.Generator$.delayedEndpoint$freechips$rocketchip$system$Generator$1(Generator.scala:89)
at freechips.rocketchip.system.Generator$delayedInit$body.apply(Generator.scala:12)
at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
at scala.App$$anonfun$main$1.apply(App.scala:76)
at scala.App$$anonfun$main$1.apply(App.scala:76)
at scala.collection.immutable.List.foreach(List.scala:381)
at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
at scala.App$class.main(App.scala:76)
at freechips.rocketchip.system.Generator$.main(Generator.scala:12)
at freechips.rocketchip.system.Generator.main(Generator.scala)
at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.lang.reflect.Method.invoke(Method.java:498)
[trace] Stack trace suppressed: run last freedomPlatforms/compile:runMain for the full output.
java.lang.RuntimeException: Nonzero exit code: 1
at scala.sys.package$.error(package.scala:27)
[trace] Stack trace suppressed: run last freedomPlatforms/compile:runMain for the full output.
[error] (freedomPlatforms/compile:runMain) Nonzero exit code: 1
[error] Total time: 11 s, completed 3 Oct, 2017 9:22:50 AM
common.mk:48: recipe for target '/home/anbuntu/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir' failed
make: *** [/home/anbuntu/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir] Error 1
But when I built TinyConfig in freedom/rocket-chip/vsim using make verilog CONFIG=TinyConfig there is no error and I could see the code is generated with accelerator. I am banging my head on this for a month now but can figure out what I am doing wrong. Can you please help me?

It was intended that Arty Dev Kit's LED 1 (rgb LED) would be the same as HiFive1's so that code written for one would more or less work on the other.

The RGB led1 assignment is wrong, should be:

Green = 19
Blue = 21
Red = 22

Also, we could make them the same polarity (on HiFive1, making the LED low turns it on).

I clone the no-pcie branch , and freedom-u-sdk with commit id b38f7c98485e78b9638a04e499d01fcb8ebf2958

When I download the bitstream to vc707, it outputs

INIT                                                    
CMD0                                                    
CMD8                                                    
ACMD41
CMD58
CMD16
CMD18
LOADING  
BOOT

and stopped...
Is my freedom-u-sdk version wrong?

i download the pre-generated mcs file from sifive's web and i download it into my fpga
the uart print the right messages and led start blinking but as i connect the jtag cable to pc the led stop blinking but i had not launch the GDB, when i unplug the jtag cable the led began blinking again

I am studying debug mechanism (JTAG with OpenOCD). I reference https://github.com/riscv/riscv-tests/tree/master/debug to figure out that. I haven't SiFive Board (e300, u500), so I want to try in Simulation (./gdbserver.py --freedom-e300-sim)

I notice that reedom/src/main/scala/everywhere/e300artydevkit/Configs.scala, maybe I could do something like that:

$ cd freedom/rocket-chip/vsim/
$ make verilog CONFIG=E300ArtyDevKitConfig
$ cd riscv-tests/debug/
$ ./gdbserver.py --freedom-e300-sim --run simv-rocketchip--E300ArtyDevKitConfig

So, what I should do to achieve that?