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Is the CPU the 6502?

Hi. I have ordered a "Bravo" kit and have been getting my head around the various opcodes.

It seems to me that ACB behaves differently to ADB SBB and SCB. The subtractions have specific microcode to preserve the original A in the B registers. ADB loads the added value into B and never changes A.

ACB0 (and ACB1) do the following as can be seen in the Microcode which ends up AO|RI e.g. it's copying the result from A.

I have tried it experimentally in the emulator which I presume is microcode driven (I have my own non microcode emulator) and it does indeed update A. e.g. if you do LDI 1 ACB 00 81 ACB 00 81 with zero memory A will not be 1 at the end.

*** Instruction ACB0 ****

PHASE 1: ---------------------------------------------------
Copy Program Counter => Memory Address Register

PHASE 2: ---------------------------------------------------
Copy Program Counter => Memory Address Register
Use High Byte MAR/PC
PHASE 3: ---------------------------------------------------
Copy RAM Memory =>
Use High Byte MAR/PC
Increment PC/MAR
PHASE 4: ---------------------------------------------------
Copy RAM Memory => B Register
Increment PC/MAR
PHASE 5: ---------------------------------------------------
Copy RAM Memory => Memory Address Register
Use High Byte MAR/PC
PHASE 6: ---------------------------------------------------
Copy B Register => Memory Address Register

PHASE 7: ---------------------------------------------------
Copy RAM Memory => B Register

PHASE 8: ---------------------------------------------------
Copy ALU A+B (Flags In) => A Register

PHASE 9: ---------------------------------------------------
Copy A Register => RAM Memory

PHASE 10: ---------------------------------------------------
Increment PC/MAR
PHASE 11: ---------------------------------------------------
Clear Instruction step

*** A Updated ***

I've been assembling the v2 ULTRA of this, and am at the point of burning the flash chips to add them. Apologies if I'm missing something obvious, but I don't see which of U6/U12/U30 goes with which of the lsb/msb/hsb files. Any help would be appreciated!

(also: I've looked through the [very helpful!] docs, but those focus on v1.6 or before --- if I get this started up, what would the baud rate for the serial port be? 115200? Something else?)

Thanks, and thanks for all the videos and interesting designs, @slu4coder .

In the listing code the following sequence occurs :

listweiter:     INW OS_PtrA
                  DEB OS_Count
                  CPI 8 BNE notmiddle
                    JPS OS_PrintSpace               ; print an extra space after 8 bytes
  notmiddle:      CPI 0 BNE nextlist
                    JPS OS_PrintEnter

This works because RTS changes A to an undefined value, which could, theoretically be 0, though I think A is set to SP.Low so it's very unlikely :) It should probably skip out past the CPI 0 test.

The "W" section "Addressing Modes" in the User Manual states Example: LDI 255 ADW 0x04 0xf0 adds 10 the the content of 0xf004 and in the case of an overflow (carry flag set) also increases address 0xf005. But this looks like it adds 255 to the content of 0xf004. Is that correct?

Since this machine is of no UART interrupt or timer-based polling mechanism for RX, the programme should take full responsibility to read out the received byte before the next one coming in. This may constrain the programme staying within a polling loop for not missing any bytes. I think a hardware flow control signal like RTS/CTS may help avoid data loss while maintaining code flexibility (the PC terminal side is with much larger TX buffer than only one byte RX buffer on this board).

I guess 2 signals within the UART receiver block can server as the RTS: the output Q of the SR latch (marked with blue frame) or the DATA_READY (DR, marked with orange frame) signal. The former one turns High after the first falling edge of RX input while the latter one turns High after the entire byte being received. And they both will not turn Low unless the received byte is read out, which makes them suitable to act as the RTS flow control signal.

I will link these wires to the CTS pin of the serial adapter and check whether this would work (as soon as I receive the chips and PCB and build up this machine). Post this issue here for discussion first.