somhi / awesome-hdl

Hardware Description Languages

Awesome Hardware Description Languages

A curated list of amazingly awesome hardware description language projects.

Hardware development

HDL doc

• Verilog IEEE Std 1364-2001, Quick Ref Guide, SystemVerilog 3.1a, Synthesizing SystemVerilog Busting the Myth that SystemVerilog is only for Verification
• VHDL standards IEEE Std 1076-2000
• SystemC standards IEEE Std 1666-2011

HDL simulators and compilers

• Verilog
  • Verilator Verilog to C++ transpiler
  • Icarus Verilog - simulator
  • Yosys - RTL synthesis
• VHDL
  • nvc - GPLv3 VHDL compiler and simulator, IEEE 1076-2002, written in C
  • GHDL - VHDL compiler and simulator, IEEE 1076-2002, written in ADA
• Lola-2
  • Oberon-2013 - Project Oberon, 2013 Edition, written in Oberon-07 License

Meta HDL and Transpilers

• C++

  • SystemC - an IEEE standard meta-HDL
  • VisualHDL - an integrated development environment (IDE) rapid design for FPGAs

• Dart

  • ROHD - A framework for hardware description and verification, 2021+

• Haskell

  • concat Haskell to hardware, 2016+
  • https://github.com/conal/talk-2015-haskell-to-hardware
  • CλaSH - A functional hardware description language
  • pipelineDSL - A Haskell DSL for describing hardware pipelines
  • Bluespec - Compiler, simulator, and tools for the Bluespec Hardware Description Language.
  • sv2v - SystemVerilog to Verilog conversion

• Java

  • jhdl ..2006
  • PSHDL

• JavaScript

  • reqack - elastic circuit toolchain
  • hdl-js - Hardware description language (HDL) parser, and Hardware simulator.
  • shdl - Simple Hardware Description Language

• Julia

  • Julia-Verilog - a Verilog-generation DSL for Julia., 2017

• OCaml

  • Hardcaml An OCaml library for designing hardware, complete with testing and simulation tools.

• Kotlin

  • Verik HDL for design and verification. generates SV. UVM.

• Python

  • HWT Meta HDL, verification env. IP-core generator, analysis tools, HDL glue
  • garnet Coarse-Grained Reconfigurable Architecture generator based on magma, 2018+
  • magma - Meta HDL, 2017+
  • migen - Meta HDL, 2011+
  • MyHDL - Process based HDL, verification framework included, 2004+
  • nMigen - A refreshed Python toolbox for building complex digital hardware, 2018+
  • Pyrope - Python-like language supporting "fluid pipelines" and "live flow", 2017+
  • PyRTL - Meta HDL, simulator suitable for research.
  • PyMTL - Process based HDL, verification framework included, 2014+
  • veriloggen - Python, Verilog centric meta HDL with HLS like features, 2015-?
  • Hdl21 - Analog HDL in Python

• Ruby

  • RHDL

• Rust

  • hoodlum - Meta HDL, 2016+
  • kaze - Meta HDL, 2019+
  • calyx - Intermediate Language (IL) for Hardware Accelerator Generators, 2020+

• Scala

  • chisel - Meta HDL, 2012+
  • SpinalHDL - Meta HDL 2012+

• C#

  • Quokka - C# to low-level RTL translator (Verilog, VHDL) and simulation toolkit examples (gates, components, RISC-V, SoC)

• Veryl

  • Veryl - An original HDL based on SystemVerilog / Rust syntax, and transplier to SystemVerilog

HLS

• hlslibs - ac_math, ac_dsp, ac_types
• legup - 2011-2015, LLVM based c->verilog
• bambu - 2003-?, GCC based c->verilog
• augh - c->verilog, DSP support
• https://github.com/utwente-fmt - abstract hls, verification libraries
• Shang - 2012-2014, LLVM based, c->verilog
• xronos - 2012, java, simple HLS
• Potholes - 2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET
• hls_recurse - 2015-2016 - conversion of recursive fn. for stackless architectures
• hg_lvl_syn - 2010, ILP, Force Directed scheduler
• abc <2008-?, A System for Sequential Synthesis and Verification
• polyphony - 2015-2017, simple python to hdl
• DelayGraph - 2016, C#, register assignment algorithms
• ahaHLS - 2019, An open source high level synthesis (HLS) tool using LLVM
• combinatorylogic/soc - 2019, An experimental System-on-Chip with a custom compiler toolchain.
• Quokka - C# to HL RTL translator
• Vitis - LLVM based, made by Xilinx. user manual

Other HDL languages

• act - asynchronous circuit/compiler tools
• autopiper
• TL-Verilog - 2015+, Supports "timing-abstract" and "transaction-level design" methodologies; supported by proprietary and open-source tools

Hardware Intermediate Representations

• CIRCT - 2020+, LLVM / MLIR framework "Circuit IR Compilers and Tools"
• coreir - 2016-?, LLVM HW compiler## License
• lgraph - 2017-?, A Multi-Language Synthesis and Simulation IR for Hardware Design
• firrtl - 2016-?, Flexible Intermediate Representation for RTL
• LLHD - Low Level Hardware Description — A foundation for building hardware design tools
• SpyDrNet - 2019+, Framework for parsing and manipulating structural netlists in Python
• VLSIR - IC Interchange Formats, defined in Google Protobuf SDL

Synthesis tools

• vtr-verilog-to-routing
• yosys - RTL synthesis framework

Visualization and Documentation generators

• bitfield - Javascript bit field diagram renderer
• d3-wave - Javascript wave graph visualizer for RTL simulations
• d3-hwschematic - Javascript hierarchical schematic visualizer for HDLs
• wavedrom - Javascript wave graph visualizer for documentations and sim.
• netlistsvg - Javascript schematic visualizer
• sphinx-hwt - Plugin for sphinx documentation generator which adds schematic into html documentation.
• Visual Debug - Custom simulation visualization framework, available within the Makerchip.com IDE.

HDL parsers

• hdlConvertor - Fast (System) Verilog/VHDL parser written as C++ extension for Python
• pyVHDLParser - VHDL parser written in Python
• rust_hdl - VHDL parser and language server written in Rust
• sv-parser - IEEE 1800-2017 System Verilog Parser written in Rust
• verible - Verible provides a SystemVerilog parser, style-linter, and formatter.

Other Simulation tools

• midas - FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
• cocotb - A coroutine based co-simulation library for writing VHDL and Verilog testbenches in Python
• osvvm - A VHDL verification framework, verification utility library, verification component library, and a simulator independent scripting flow

Other Design Automation tools

• RgGen - Code generator tool to generate RTL, UVM RAL models and Wiki documents from CSR specifications
• sv-tests - Test suite designed to check compliance with the SystemVerilog standard
• tbengy - Code generator tool to generate SV/UVM RTL and Testbech as well scripts with support for bitstream generation for Digilent FPGAs

License

To the extent possible under law, Aliaksei Chapyzhenka has waived all copyright and related or neighboring rights to this work.