soniccd123 / snes-feram-cart Goto Github PK

What problems can I have? I have pcb model january but if the pin 20 is wrong, can I solution this problem? Is a important problem? Sorry for my english, I hope you understand my cuestion. Thanks

Hi sonnic,

I would like to use FM16W08-SG (64Kbit).
I see that only pin 1 and pin 26 are not used with FM16W08.
Should I do something else with FM16W08 when its for Hirom or Lorom use?
Will adress pins changes for FM16W08-SG if I will use it for Hirom or Lorom game? (Like in the case of FM18W08).
Or all I need to do Is just tied all pins to respective address names, except pin 1 and 26 (that need to be tied to GND).
I dont understand why for 256Kbit FRAM we need to have different pin connection for HiROM and LoROM ?
And for other size like 64Kbit and 16Kbit one schema for both?
Here is my visual schematic how to connect SNES for FRAM like FM16W08, FM18W08,
or use one of them (FM16W08 or FM18W08) like 16Kbit size FRAM.
Can you confirm me if you think that it will works?

Thank you for help.

Thanks for your nice project. I'm reading your schematic yesterday, with an SNES cart mapping doc on "http://gatchan.net/uploads/Consoles/SNES/Flashcard/SNES_MemMap.txt"
and "https://wiki.superfamicom.org/schematics-ports-and-pinouts"

I found the SRAM mapping is different from what the doc described. So I create this issue to request your help on confirming if it's intended or just small fault on drawing schematic.

(All address pin name below is referencing to CartSlot pin name, not the NET name in your KiCAD project.)

HiROM mode

With this doc the SRAM enable logic equation in "HiROM mode" is:

!SRAM_CE = (!A15 & BA5 & A14 & A13) & (!nCART & nRESET)
or 
!SRAM_CE = (!BA6 & BA5 & A14 & A13) & (!nCART & nRESET)

and the SRAM should be mapped to segment $20-$3F and $A0-$BF.

When JP1-JP5 shorted with pin1-pin2.(Enable HiROM mode)
Focusing on the part (!A15 & BA5 & A14 & A13) or (!BA6 & BA5 & A14 & A13):

• 4071-U2A part is corresponding to (!A15 and !BA6) which is OK for general adaption.
• 4081-U1A part is corresponding to (A14 & A13).
• But for 4081-U1B part, the equation in your schematic is (BA4 & BA5). Which contains an additional BA4.
  This makes the SRAM be mapped to segment $30-$3F and $B0-$BF. Which is different from the known doc.

LoROM mode

With this doc the SRAM enable logic equation in "LoROM mode" is:

!SRAM_CE = (Vcc & BA5 & BA4 & !A15) & (!nCART & nRESET)
or 
!SRAM_CE = (BA6 & BA5 & BA4 & !A15) & (!nCART & nRESET)

and the SRAM should be mapped to segment $70-$7D and $F0-$FF.

When JP1-JP5 shorted with pin3-pin2.(Enable LoROM mode)
Focusing on the part (Vcc & BA5 & BA4 & !A15) or (BA6 & BA5 & BA4 & !A15):

• JP4 connected to /CART filtered segment $7E-$7F. That's ok.
• 4081-U1A part is corresponding to (!A15). That's ok.
• But for 4081-U1B part the equation in your schematic is (BA6 & BA5). So the BA4 is missed in expression.
  This makes the SRAM be mapped to segment $60-$7D and $E0-$FF. Which is different from the known doc.

My modification

If the above problem is indeed mistake in drawing. I think the modification can be like below.

The solution A uses the expression (BA6 & BA5 & BA4 & !A15) in LoROM mode. It requires an additional AND gate. So I added an 4081. Or it can be achieved with an 3-input AND gate with BA4 BA5 BA6 as input.

The solution A uses the expression (Vcc & BA5 & BA4 & !A15), so the Vcc can be skipped in AND. The additional AND gate component can be saved. The jumper can also be moved to right of the 4081, thus the +5V Vcc can be skipped for HiROM mode.
(Note: I'm still not clear if (Vcc & BA5 & BA4 & !A15) can be apply to all game, as I think this constraint is more wide than adding BA6. I'm not sure if it will interfere other logic in the corresponding page. I'm not that familiar with SNES.)

Hi.
I have made a number of these but I can't get any of them to work.
I am trying V3.1.
I am trying many HiROM images and have all the jumpers set to H.
I have all the dip switches turned on.

I have a wire jumper from pin 1 to pin 20 of U5 to fix the missing 5v connection to pin 20 of U5. Is this correct?
Can I confirm that the silk screen for U1, U2 and U7 is the wrong way around and all of these chips have their pin 1 closest to the left side of the board where the dip switches are? That is opposite to the U labels on the silk screen.
Are any other markings on the silk screen wrong?

When you say "byte swapped" do you mean byte swapped using a tool like Wasabi or do you mean 16bit endian byte swapped? I have tried both and neither worked.

I know that my CIC chip works as it works successfully in other designs.

I don't know what to try next. All attempt give a black screen.

I have built other peoples designs without issue but can't seem get this one to work.
Any help or advice would be greatly appreciated.
I want to use this design as it has many desirable features and looks like it is the best one yet.

Oh, and another little thing. In the README.dm in the paragraph about bank switching it talks about the Sega Genesis and not the SNES.

Thanks.

Have you tried your Kicad PCB?
U5 has no +5 power connected to pin 20.
Perhaps the CMOS just works?

Can tsop be used with an adapter? If so, what tsop model could I use? The m27c322 is giving me problems when ordering them, 3 out of 5 don't work.
Thanks and regards.