Unsupported compressed instruction on VexRiscvAxi4LinuxPlicClint.scala about vexriscv

[PedroAntunes178]

This happens on current master branch with sbt version:

sbt version in this project: 1.6.0
sbt script version: 1.8.2

[PedroAntunes178]

Already noticed the comment in the documentation.

If you get a Missing inserts : INSTRUCTION_ANTICIPATE error, that's because the RegFilePlugin is configured to use SYNC memory read ports to access the register file, but the IBus plugin configuration can't provide the instruction's register file read address one cycle before the decode stage. To workaround that you can :

    Configure the RegFilePlugin to implement the register file read in a asyncronus manner (ASYNC), if your target device support such things
    If you use the IBusSimplePlugin, you need to enable the injectorStage configuration
    If you use the IBusCachedPlugin, you can either enable the injectorStage, or set twoCycleCache + twoCycleRam to false.

Thank you.

[Dolu1990]

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