Comments (5)
Hi,
Personnaly, i reversed engineered them from various software drivers out there in the wild XD
Bit a paine in the ass.
They are in the SpinalHDL repository
from vexriscv.
https://github.com/SpinalHDL/SpinalHDL/blob/645e03f21326f9baffe49ac4c59cff2ea6e86cd3/lib/src/main/scala/spinal/lib/misc/plic/PlicMapper.scala#L37
https://github.com/SpinalHDL/SpinalHDL/blob/645e03f21326f9baffe49ac4c59cff2ea6e86cd3/lib/src/main/scala/spinal/lib/misc/Clint.scala#L49
from vexriscv.
https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/driver/plic.h
https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/driver/clint.h
from vexriscv.
Hi,
Are we ablle to set the MTIME FREQ, in the CLINT?
From looking at the Scala, it seems the MTIMER counter increments every clock cycle. Would it be possible to define in the VexRiscv Scala file that the internal timer frequency is 100 KHz? Therefore, the MTIMER counter would only increment every CLK_FREQ / MTIME_FREQ
clock cycles.
from vexriscv.
Hi,
would need to modify the clint implemention, would not be complicated
from vexriscv.
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