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Dolu1990 avatar Dolu1990 commented on June 20, 2024

Hi

Have you seen this doc ? :
https://github.com/SpinalHDL/VexRiscv/tree/master/doc/nativeJtag
Which bscane2 id did you used ?

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ztachip avatar ztachip commented on June 20, 2024

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Dolu1990 avatar Dolu1990 commented on June 20, 2024

Ahh i would say you would have two ways,
Either you expose the jtag instruction interface (bscane like) which can be then bridged to something else. And in the case you want to bridge it from a true 4 pins jtag, you just need to create a little jtag tap which "behave like the bscane2"

Something like :

       val jtag = slave(new Jtag())
        val jtagClockDomain = ClockDomain(jtag.tck) on new Area
          val tap = new JtagTap(jtag, 6)
          val idcodeArea = tap.idcode(B(p.tapId, 32 bits))(5)
          val wrapper = tap.map(debug.jtagInstruction, instructionId = 8)
        }
        

Either you expose the native vex debug interface, which is a small memory bus, and then you provide the bridge from what ever -> to it.

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