Assertion when tracing the elaboration issue about vexriscv

[eruanno123]

Btw. "vexriscv.custom.Risky" is a copy of "Briey" with my customization to the peripherals. As I mentioned, I will try to provide an example of the issue, once I strip it down from many things unrelated to the main issue.

[eruanno123]

The reasonable workaround I just found is enabling the traces during the first pass by providing debugComponents to the SpinalConfig:

val debugComponents = HashSet[Class[_]]()
debugComponents += this.getClass()

val config =
  SpinalConfig(
    /*... */,
    debugComponents = debugComponents
  )

config.generateVerilog({
  val toplevel = new Risky(riskyConfig.copy(sdramLayout = IS42x160G.layout))
  toplevel
})

Now, I get correct elaboration failure results

[info] [Progress] at 1.721 : Checks and transforms
[error] Exception in thread "main" spinal.core.SpinalExit: 
[error]  Error detected in phase PhaseCheck_noLatchNoOverride
[error] ********************************************************************************
[error] ********************************************************************************
[error] NO DRIVER ON (toplevel/axi_bootManager/aclk : in Bool), defined at
[error] ???
[error] ********************************************************************************
[error] ********************************************************************************
[error] NO DRIVER ON (toplevel/axi_bootManager/aresetn : in Bool), defined at
[error] ???

[Dolu1990]

Hi,

The reasonable workaround I just found is enabling the traces during the first pass by providing debugComponents to the SpinalConfig:

How was your scala main which was generating the hardware before ?
The issue you had will happen if you define the VexRiscv config outside the generateVerilog block.

Was it the case ?

[eruanno123]

Thanks for the quick response.

I think this might be the case, although I am not sure if making a copy of the configuration counts. I am building the configuration starting from defaults and 'injecting' modifications passed through the command line. I will check if it helps to refactor the code, so that things happen under the generateVerilog block.

class CommandLineConf(arguments: Seq[String]) extends ScallopConf(arguments) {
  val outputDir = opt[String]("output", short = 'O', default = Some("_build"))
  val hwJtag = toggle("hw-jtag")
  val coreFrequency = opt[Int](
    "core-frequency",
    default = Some(100000000),
    validate = (0 to 300000000).contains
  )

  val makeIntRangeArg =
    (name: String, default: Some[Int], minVal: Int, maxVal: Int) =>
      opt[Int](name, default = default, validate = (minVal to maxVal).contains)

  val makeApbAddressArg = (id: Int) =>
    makeIntRangeArg(s"apb${id}-address-width", Some(21), 12, 32)

  val apb1AddressWidth = makeApbAddressArg(1)
  val apb2AddressWidth = makeApbAddressArg(2)

  val noDma = toggle("no-dma")

  verify()

  def propagateRiskyConfig(baseConfig: RiskyConfig): RiskyConfig = {
    baseConfig.copy(
      useHardwareJtag = hwJtag.toOption.getOrElse(false),
      axiFrequency = coreFrequency.toOption.getOrElse(100000000) Hz,
      apb1BusConfig = RiskyConfig.default.apb1BusConfig
        .copy(addressWidth = apb1AddressWidth.toOption.getOrElse(21)),
      apb2BusConfig = RiskyConfig.default.apb2BusConfig
        .copy(addressWidth = apb2AddressWidth.toOption.getOrElse(21)),
      saxi1BusPresent = !noDma.toOption.getOrElse(false)
    )
  }

  def getOutputBuildDirectory(): String = outputDir.toOption.get
}

// Implementation for Terasic DE0-Nano board
object RiskyDe0Nano {
  def main(args: Array[String]) {
    val cmdLineConfig = new CommandLineConf(args)
    val riskyConfig = cmdLineConfig.propagateRiskyConfig(RiskyConfig.default)
 
   // ... here is some irrelevant SDRAM stuff

    val debugComponents = HashSet[Class[_]]()
    debugComponents += this.getClass()

    val config =
      SpinalConfig(
        targetDirectory = cmdLineConfig.getOutputBuildDirectory(),
        debugComponents = debugComponents
      )

    config.generateVerilog({
      val toplevel =
        new Risky(riskyConfig.copy(sdramLayout = IS42x160G.layout))
      toplevel
    })
  }
}

[eruanno123]

I am confirming this is indeed the reason I am observing the issue. The following modification works as intended:

    config.generateVerilog({
      // moved riskyConfig here:
      val riskyConfig = cmdLineConfig.propagateRiskyConfig(RiskyConfig.default)
      val toplevel =
        new Risky(riskyConfig.copy(sdramLayout = IS42x160G.layout))
      toplevel
    })

Many thanks for help!