EmbeddedRiscvJtag synthesis issue about vexriscv

[Dolu1990]

Hi,

Thanks for the issue ^^
First time i hear of something like it + the jtag stuff didn't changed since a quite long time, so it may be a yosys bug ?
Would have to check the netlist i guess.

Are tap_fsm_state still in the netlist after yosys ? (without the added = 0) ?

[gregdavill]

It seems like when an initial value is provided the register isn't considered for one-hot translation by yosys step FSM_EXTRACT

Not marking orbtrace_mini.VexRiscv.debugTransportModuleJtagTap_1.tap_fsm_state as FSM state register:
    Register has an initialization value.

This can also be achieved with

  (* fsm_encoding = "none" *) reg        [3:0]    tap_fsm_state;

Curiously if I add the reset state and don't just rely on the default clause for it in the tap_state case statement:

      JtagState_RESET : begin
        _zz_tap_fsm_stateNext_16 = _zz_tap_fsm_stateNext;
      end

Yosys report this in the log. The resulting bitstream works on the FPGA.

Not marking orbtrace_mini.VexRiscv.debugTransportModuleJtagTap_1.tap_fsm_state as FSM state register:
    Circuit seems to be self-resetting.

Given that the addition of the JtagState_RESET state to the case shouldn't actually change anything logic wise I'm pretty sure the absence of it might be causing this issue. This is probably also tied into the fact that all 16 states are legal, and the TAP doesn't require a reset signal, which might make it un-suitable for this FSM extraction in yosys.

[Dolu1990]

gg for the debug ^^

So, changing :

  val stateNext = JtagState()
  val state = RegNext(stateNext) randBoot()
  stateNext := state.mux(
    default    -> (jtag.tms ? RESET     | IDLE),           //RESET
    IDLE       -> (jtag.tms ? DR_SELECT | IDLE),
    IR_SELECT  -> (jtag.tms ? RESET     | IR_CAPTURE),
    IR_CAPTURE -> (jtag.tms ? IR_EXIT1  | IR_SHIFT),
    IR_SHIFT   -> (jtag.tms ? IR_EXIT1  | IR_SHIFT),
    IR_EXIT1   -> (jtag.tms ? IR_UPDATE | IR_PAUSE),
    IR_PAUSE   -> (jtag.tms ? IR_EXIT2  | IR_PAUSE),
    IR_EXIT2   -> (jtag.tms ? IR_UPDATE | IR_SHIFT),
    IR_UPDATE  -> (jtag.tms ? DR_SELECT | IDLE),
    DR_SELECT  -> (jtag.tms ? IR_SELECT | DR_CAPTURE),
    DR_CAPTURE -> (jtag.tms ? DR_EXIT1  | DR_SHIFT),
    DR_SHIFT   -> (jtag.tms ? DR_EXIT1  | DR_SHIFT),
    DR_EXIT1   -> (jtag.tms ? DR_UPDATE | DR_PAUSE),
    DR_PAUSE   -> (jtag.tms ? DR_EXIT2  | DR_PAUSE),
    DR_EXIT2   -> (jtag.tms ? DR_UPDATE | DR_SHIFT),
    DR_UPDATE  -> (jtag.tms ? DR_SELECT | IDLE)
  )

into :

  val stateNext = JtagState()
  val state = RegNext(stateNext) randBoot()
  stateNext := state.mux(
    default    -> (jtag.tms ? RESET     | IDLE),           //RESET
    RESET      -> (jtag.tms ? RESET     | IDLE),   // <---------------------------- adding this line 
    IDLE       -> (jtag.tms ? DR_SELECT | IDLE),
    IR_SELECT  -> (jtag.tms ? RESET     | IR_CAPTURE),
    IR_CAPTURE -> (jtag.tms ? IR_EXIT1  | IR_SHIFT),
    IR_SHIFT   -> (jtag.tms ? IR_EXIT1  | IR_SHIFT),
    IR_EXIT1   -> (jtag.tms ? IR_UPDATE | IR_PAUSE),
    IR_PAUSE   -> (jtag.tms ? IR_EXIT2  | IR_PAUSE),
    IR_EXIT2   -> (jtag.tms ? IR_UPDATE | IR_SHIFT),
    IR_UPDATE  -> (jtag.tms ? DR_SELECT | IDLE),
    DR_SELECT  -> (jtag.tms ? IR_SELECT | DR_CAPTURE),
    DR_CAPTURE -> (jtag.tms ? DR_EXIT1  | DR_SHIFT),
    DR_SHIFT   -> (jtag.tms ? DR_EXIT1  | DR_SHIFT),
    DR_EXIT1   -> (jtag.tms ? DR_UPDATE | DR_PAUSE),
    DR_PAUSE   -> (jtag.tms ? DR_EXIT2  | DR_PAUSE),
    DR_EXIT2   -> (jtag.tms ? DR_UPDATE | DR_SHIFT),
    DR_UPDATE  -> (jtag.tms ? DR_SELECT | IDLE)
  )

would fix it ?

[Dolu1990]

(conceptualy, because SpinalHDL will complain that :

UNREACHABLE DEFAULT STATEMENT on
spinal.lib.com.jtag.JtagFsm.(JtagTap.scala:67)

[Dolu1990]

  val stateNext = JtagState()
  val state = RegNext(stateNext) randBoot()
  switch(state, coverUnreachable = true){
    default(stateNext := jtag.tms ? RESET | IDLE)
    def add(k : JtagState.E, t : JtagState.E, f : JtagState.E) = is(k)(stateNext := jtag.tms.mux(t, f))
    add(RESET     , RESET    , IDLE)
    add(IDLE      , DR_SELECT, IDLE)
    add(IR_SELECT , RESET    , IR_CAPTURE)
    add(IR_CAPTURE, IR_EXIT1 , IR_SHIFT)
    add(IR_SHIFT  , IR_EXIT1 , IR_SHIFT)
    add(IR_EXIT1  , IR_UPDATE, IR_PAUSE)
    add(IR_PAUSE  , IR_EXIT2 , IR_PAUSE)
    add(IR_EXIT2  , IR_UPDATE, IR_SHIFT)
    add(IR_UPDATE , DR_SELECT, IDLE)
    add(DR_SELECT , IR_SELECT, DR_CAPTURE)
    add(DR_CAPTURE, DR_EXIT1 , DR_SHIFT)
    add(DR_SHIFT  , DR_EXIT1 , DR_SHIFT)
    add(DR_EXIT1  , DR_UPDATE, DR_PAUSE)
    add(DR_PAUSE  , DR_EXIT2 , DR_PAUSE)
    add(DR_EXIT2  , DR_UPDATE, DR_SHIFT)
    add(DR_UPDATE , DR_SELECT, IDLE)
  }

Would fix it.

So, that would be good for you ?

that would only change the generated verilog by adding the :

  JtagState_RESET : begin
    _zz_tap_fsm_stateNext_16 = _zz_tap_fsm_stateNext;
  end

[gregdavill]

Thanks for the fix on the Scala side. Yes, atleast from my editing of the verilog with exactly that line seems to fix the issue encountered by Yosys.

I'd be inclined to remove the default case if it's guaranteed that state/StateNext are 4 bits in size, since the default will never be reached as the case statements cover all possible states. But I'm not too familiar with SpinalHDL, so I'll defer that to you.

[Dolu1990]

Fixed with SpinalHDL/SpinalHDL@2c5e826

It keep the default case empty and add the reset case.
Thanks for the issue ^^