CPU exception signal about vexriscv

[Dolu1990]

divide by 0 is legal in RISC-V :D
So let's say you fetch a illegal instruction => exception.

CsrPlugin_exceptionPortCtrl is containing all the logic which on each stage will aggregate new exceptions requests, and pipeline the exception downward.
CsrPlugin_exceptionPortCtrl_exceptionContext_code is the signal which is at the end of the pipeline and specify the nature of the exception (if one happened, which is specify by the last element of exceptionValids)

[snowprogrammer]

divide by 0 is legal in RISC-V :D So let's say you fetch a illegal instruction => exception.

CsrPlugin_exceptionPortCtrl is containing all the logic which on each stage will aggregate new exceptions requests, and pipeline the exception downward. CsrPlugin_exceptionPortCtrl_exceptionContext_code is the signal which is at the end of the pipeline and specify the nature of the exception (if one happened, which is specify by the last element of exceptionValids)

So If I want to detect all the exception event, can I use "CsrPlugin_exceptionPortCtrl_exceptionContext_code" as a detector like
if code=="xxx" then event==exception? @Dolu1990

[Dolu1990]

No you can't because the value the code is undefined when there is no exception.
Instead you can use
if(CsrPlugin_hadException)then event = CsrPlugin_exceptionPortCtrl_exceptionContext_code