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Apb2CSTrgt register description JSON schema is a subset of RDL; RDL could be generated to allow integration with third-party/commercial tools.

Describe the bug
The Simple example is not intact, line coverage is <100%.

To Reproduce
Steps to reproduce the behavior:
Run test with Verilator

Expected behavior
Simple example needs a test which invokes PSLVERR response.

Desktop (please complete the following information):

• OS: Any

Additional context
Add any other context about the problem here.

You can already generate nice Bundles IO named after the JSON specified bit-fields. These can be used to wrap Apb2CSTrgt Modules connecting the anonymous, numbered MixedVec IO to the named Bundle IO in order. But why not just generate the whole Wrapper Module with the Bundles.

There is currently no unit test for the Apb2CSTrgt module's W1C bit-field mode. A test should be written, parameterizing the module with a JSON register description describing some registers with W1C bit-fields. The parameterized instance should be wrapped in a module with named inputs corresponding to the W1C bit-fields. The test should drive the inputs corresponding to the W1C register bit-fields with single-cycle pulses to set the register bits to '1'. The register bit-fields should be read via the APB2 target to check that the bit(s) were set to '1'. The register bit-fields which have been set to '1' should be written to with a '1' to clear them to '0'. The same register bit-fields should be read again to check that they have indeed been cleared. Setting and clearing individual bits of each field should be tested as well as set/clear of multiple bits simultaneously. A negative test should be performed to check that writing '0' to the register bit-fields has no side-effect (i.e. does not actually clear the corresponding bit to '0', but does nothing).

From AMBA APB Protocol Specification
pProt[0]

• LOW indicates normal access
• HIGH indicates privileged access

pProt[1]

• LOW indicates a secure access
• HIGH indicates a non-secure access

The JSON register description schema should be extended to allow a register to be marked as either privileged only or secure only or both. If the corresponding mode was not indicated on pProt[1:0] then the register would be neither writable nor readable (would read zero) and pSlvErr would be signaled to the initiator.

There is no requirement to do anything in particular with pProt[2] which is intended to hint whether the access is an instruction access or a data access.

Initially running all tests with Treadle then migrating to Verilator to allow coverage report generation and PR gating if coverage drops.

Ideally a very simple example of Apb2CSTrgt for each register mode, with tests. Ultimately a realistic fully fledged example, perhaps driving and connected to status some simple external logic (e.g. a simple timer or counter).

The Apb2CSTrgt module supports pStrb as described in Apb2CSTrgt.scala:

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"if a bit field straddles two or more byte lanes and not ALL the corresponding bits of pStrb are set then the bit field is not written (at all) and pSlvErr is signalled. In other words, partial writes to bitfields are not supported; either the whole bit field is written, when ALL corresponding pStrb bits are set, or the bit field is not written at all. Writing to a register with NONE of the pStrb bits corresponding to a given bit field set is OK and is NOT an error condition. This is a design decision."

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None of the above is currently exhaustively tested.

There is currently no test targeting the read-only bit-field mode supported by Apb2CSTrgt. The test should instantiate Apb2CSTrgt with a JSON register description describing some registers with RO bit fields. The test should include a wrapper module with named inputs for the RO bit-fields and drive those inputs with known values, and check that the same values are readable via the APB2 target on the corresponding bit-fields. It should also perform a negative check, that the registers are not writable.

Something easily digestible