sybreon / dcpu16 Goto Github PK

Hello,
I've been working on a behavioral model of the DCPU-16 in SystemVerilog. You might want to have a look - my idea is that this model would be useful to have in a testbench for a RTL implementation of the dcpu16. (I started working on my own RTL implementation, but realized testing would be much easier if I had a trusted reference to compare results with.)

In the tests for the model itself, I'm using swetland/dcpu16 as a reference - testing is certainly not complete, but I have a decent framework for building a test suite onto.

https://github.com/aaronferrucci/dcpu16-model-SystemVerilog

Comments welcome!

thanks,
-Aaron
P.S. I'm new to github - if I've committed a breach of etiquette by creating an "issue", apologies in advance, and I welcome your recommendation for the proper way to say, "hey, check out this repo".